Inventor
VADEN MICHAEL THOMAS
US17 patents
⚠️ This page may combine multiple inventors who share the name “VADEN MICHAEL THOMAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
16 patentsUS6832329B2Dec 14, 2004
Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failures
IBM53 citations95
US6401192B1Jun 4, 2002
Apparatus for software initiated prefetch and method therefor
IBM75 citations95
US5758119AMay 26, 1998
System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache
IBM55 citations95
US5740399AApr 14, 1998
Modified L1/L2 cache inclusion for aggressive prefetch
IBM63 citations95
US7818550B2Oct 19, 2010
Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system
IBM25 citations92
US6430680B1Aug 6, 2002
Processor and method of prefetching data based upon a detected stride
IBM29 citations92
US6275918B1Aug 14, 2001
Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold
IBM32 citations91
US7809924B2Oct 5, 2010
System for generating effective address
IBM15 citations81
US5822556AOct 13, 1998
Distributed completion control in a microprocessor
IBM10 citations73
US7376890B2May 20, 2008
Method and system for checking rotate, shift and sign extension functions using a modulo function
IBM6 citations72
US7360058B2Apr 15, 2008
System and method for generating effective address
IBM6 citations71
US6178493B1Jan 23, 2001
Multiprocessor stalled store detection
IBM14 citations71
US6914849B2Jul 5, 2005
Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders
IBM8 citations69
US8024647B2Sep 20, 2011
Method and system for checking rotate, shift and sign extension functions using a modulo function
IBM4 citations61
US7991816B2Aug 2, 2011
Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units
IBM0 citations49
US7509365B2Mar 24, 2009
Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units
IBM0 citations49