Inventor

KIM DU-EUNG

KR98 patents

⚠️ This page may combine multiple inventors who share the name “KIM DU-EUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM DU-EUNG

SAMSUNG ELECTRONICS CO LTD

Layout structure in semiconductor memory device comprising global work lines, local work lines, global bit lines and local bit lines

Semiconductor memory device having a three-dimensional cell array structure

Phase change memories and/or methods of programming phase change memories using sequential reset control

Phase-change memory device and method of writing a phase-change memory device

Phase random access memory with high density

Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device

Phase-change random access memory (PRAM) performing program loop operation and method of programming the same

Method of programming a memory cell array using successive pulses of increased duration

Phase-change memory device and method of writing a phase-change memory device

Phase change random access memory (PRAM) device having variable drive voltages

Phase-change memory device

Phase-change semiconductor memory device and method of programming the same

Phase change random access memory device having variable drive voltage circuit

Method for programming phase-change memory array to set state and circuit of a phase-change memory device

Phase change random access memory (PRAM) device

Memory device with reduced word line resistance

Reference voltage generating circuit using active resistance device

Parallel test circuit for semiconductor memory

Phase-changeable memory device and method of programming the same

Semiconductor memory device with stacked control transistors

Phase change memory devices employing cell diodes and methods of fabricating the same

Phase-changeable memory device and read method thereof

PRAM and method of firing memory cells

Multilevel nonvolatile memory device using variable resistance

Semiconductor memory device and data error detection and correction method of the same

Nonvolatile memory device and related methods of operation

Nonvolatile memory device using variable resistive element

Phase change memory device and related programming method

Phase change memory devices and program methods

Phase change memory device and program method thereof

Phase change memory device using multiprogramming method

Non-volatile memory devices and systems including phase-change one-time-programmable (OTP) memory cells and related methods

Phase change memory device and method of driving word line thereof

Phase change memory device

Nonvolatile memory devices having enhanced bit line and/or word line driving capability

Redundancy circuit in semiconductor memory device having a multiblock structure

Semiconductor device having resistance based memory array, method of reading, and systems associated therewith

Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith

Resistance variable memory device reducing word line voltage

Apparatus and systems using phase change memories

Phase-change memory device and method of fabricating the same

Initial firing method and phase change memory device for performing firing effectively

Flip chip interface circuit of a semiconductor memory device

Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same

Semiconductor memory device

KIM SUNG-MIN

Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell

CHO WOO-YEONG

Method of driving multi-level variable resistive memory device and multi-level variable resistive memory device

CHOI BYUNG-GIL

Multi-level nonvolatile memory device using variable resistive element

LEE KWANG-JIN

Semiconductor memory device and data error detection and correction method of the same

SAMSUNG ELECTRONCIS CO LTD

Phase change random access memory device and related methods of operation