Inventor
KEMERER DOUGLAS W
US17 patents
⚠️ This page may combine multiple inventors who share the name “KEMERER DOUGLAS W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
15 patentsUS5051917ASep 24, 1991
Method of combining gate array and standard cell circuits on a common semiconductor chip
IBM52 citations93
US7076749B2Jul 11, 2006
Method and system for improving integrated circuit manufacturing productivity
IBM22 citations89
US5369595ANov 29, 1994
Method of combining gate array and standard cell circuits on a common semiconductor chip
IBM24 citations89
US7397228B2Jul 8, 2008
Programmable on-chip sense line
IBM22 citations88
US7696811B2Apr 13, 2010
Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
IBM9 citations81
US7459958B2Dec 2, 2008
Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
IBM14 citations81
US7504847B2Mar 17, 2009
Mechanism for detection and compensation of NBTI induced threshold degradation
IBM12 citations79
US4786613ANov 22, 1988
Method of combining gate array and standard cell circuits on a common semiconductor chip
IBM22 citations79
US7146596B2Dec 5, 2006
Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid
IBM10 citations71
US6426890B1Jul 30, 2002
Shared ground SRAM cell
IBM10 citations71
US7849426B2Dec 7, 2010
Mechanism for detection and compensation of NBTI induced threshold degradation
IBM6 citations62
US7619398B2Nov 17, 2009
Programmable on-chip sense line
IBM4 citations62
US7941780B2May 10, 2011
Intersect area based ground rule for semiconductor design
IBM2 citations59
US7671666B2Mar 2, 2010
Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
IBM1 citations49
US7490303B2Feb 10, 2009
Identifying parasitic diode(s) in an integrated circuit physical design
IBM0 citations49