Inventor
SEIBERT EDWARD W
US7 patents
⚠️ This page may combine multiple inventors who share the name “SEIBERT EDWARD W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
5 patentsUS5761080AJun 2, 1998
Method and apparatus for modeling capacitance in an integrated circuit
IBM68 citations94
US6430729B1Aug 6, 2002
Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing
IBM34 citations89
US6473887B1Oct 29, 2002
Inclusion of global wires in capacitance extraction
IBM4 citations61
US6519752B1Feb 11, 2003
Method of performing parasitic extraction for a multi-fingered transistor
IBM6 citations59
US7490303B2Feb 10, 2009
Identifying parasitic diode(s) in an integrated circuit physical design
IBM0 citations49