Inventor
TSENG PIN-NAN
TW19 patents
⚠️ This page may combine multiple inventors who share the name “TSENG PIN-NAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
13 patentsUS5575706ANov 19, 1996
Chemical/mechanical planarization (CMP) apparatus and polish method
TAIWAN SEMICONDUCTOR MFG255 citations97
US5702982ADec 30, 1997
Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
TAIWAN SEMICONDUCTOR MFG117 citations96
US5756396AMay 26, 1998
Method of making a multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect
TAIWAN SEMICONDUCTOR MFG72 citations95
US6448649B1Sep 10, 2002
Multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect
TAIWAN SEMICONDUCTOR MFG25 citations92
US5801096ASep 1, 1998
Self-aligned tungsen etch back process to minimize seams in tungsten plugs
TAIWAN SEMICONDUCTOR MFG22 citations92
US5723893AMar 3, 1998
Method for fabricating double silicide gate electrode structures on CMOS-field effect transistors
TAIWAN SEMICONDUCTOR MFG87 citations91
US5547881AAug 20, 1996
Method of forming a resistor for ESD protection in a self aligned silicide process
TAIWAN SEMICONDUCTOR MFG35 citations91
US5521121AMay 28, 1996
Oxygen plasma etch process post contact layer etch back
TAIWAN SEMICONDUCTOR MFG22 citations87
US6169314B1Jan 2, 2001
Layout pattern for improved MOS device matching
TAIWAN SEMICONDUCTOR MFG8 citations74
US5952698ASep 14, 1999
Layout pattern for improved MOS device matching
TAIWAN SEMICONDUCTOR MFG13 citations74
US5712207AJan 27, 1998
Profile improvement of a metal interconnect structure on a tungsten plug
TAIWAN SEMICONDUCTOR MFG14 citations72
US5411907AMay 2, 1995
Capping free metal silicide integrated process
TAIWAN SEMICONDUCTOR MFG17 citations69
US5866481AFeb 2, 1999
Selective partial curing of spin-on-glass by ultraviolet radiation to protect integrated circuit dice near the wafer edge
TAIWAN SEMICONDUCTOR MFG3 citations62
TAIWAN SEMICONDUCTOR MFG CO LTD
6 patentsUS9728453B2Aug 8, 2017
Methods for hybrid wafer bonding integrated with CMOS processing
TAIWAN SEMICONDUCTOR MFG CO LTD21 citations94
US9711555B2Jul 18, 2017
Dual facing BSI image sensors with wafer level stacking
TAIWAN SEMICONDUCTOR MFG CO LTD31 citations94
US11037978B2Jun 15, 2021
Dual facing BSI image sensors with wafer level stacking
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US10510597B2Dec 17, 2019
Methods for hybrid wafer bonding integrated with CMOS processing
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations73
US10453889B2Oct 22, 2019
Dual facing BSI image sensors with wafer level stacking
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US11894408B2Feb 6, 2024
Dual facing BSI image sensors with wafer level stacking
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations63