P

Inventor

WILLIAMS DEREK E

US202 patents
⚠️ This page may combine multiple inventors who share the name “WILLIAMS DEREK E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

40 patents
US6748501B2Jun 8, 2004

Microprocessor reservation mechanism for a hashed address system

IBM59 citations96
US10067713B2Sep 4, 2018

Efficient enforcement of barriers with respect to memory move sequences

IBM17 citations94
US9785557B1Oct 10, 2017

Translation entry invalidation in a multithreaded data processing system

IBM23 citations94
US9696928B2Jul 4, 2017

Memory transaction having implicit ordering effects

IBM38 citations94
US9575815B1Feb 21, 2017

Translation entry invalidation in a multithreaded data processing system

IBM25 citations94
US7475191B2Jan 6, 2009

Processor, data processing system and method for synchronizing access to data in shared memory

IBM33 citations93
US7447845B2Nov 4, 2008

Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality

IBM29 citations92
US9772945B1Sep 26, 2017

Translation entry invalidation in a multithreaded data processing system

IBM9 citations84
US9710394B2Jul 18, 2017

Translation entry invalidation in a multithreaded data processing system

IBM10 citations84
US9632942B2Apr 25, 2017

Expedited servicing of store operations in a data processing system

IBM6 citations84
US9501411B2Nov 22, 2016

Cache backing store for transactional memory

IBM8 citations84
US9430166B2Aug 30, 2016

Interaction of transactional storage accesses with other atomic semantics

IBM6 citations84
US9396127B2Jul 19, 2016

Synchronizing access to data in shared memory

IBM8 citations84
US9390026B2Jul 12, 2016

Synchronizing access to data in shared memory

IBM7 citations84
US8930629B2Jan 6, 2015

Data cache block deallocate requests in a multi-level cache hierarchy

IBM7 citations84
US7818511B2Oct 19, 2010

Reducing number of rejected snoop requests by extending time to respond to snoop request

IBM12 citations84
US7716428B2May 11, 2010

Data processing system, cache system and method for reducing imprecise invalid coherency states

IBM8 citations84
US7444494B2Oct 28, 2008

Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction

IBM14 citations84
US7404046B2Jul 22, 2008

Cache memory, processing unit, data processing system and method for filtering snooped operations

IBM8 citations74
US11106608B1Aug 31, 2021

Synchronizing access to shared memory by extending protection for a target address of a store-conditional request

IBM3 citations73
US10997075B2May 4, 2021

Adaptively enabling and disabling snooping bus commands

IBM1 citations73
US10977183B2Apr 13, 2021

Processing a sequence of translation entry invalidation requests with regard to draining a processor core

IBM2 citations73
US10817434B2Oct 27, 2020

Interruptible translation entry invalidation in a multithreaded data processing system

IBM3 citations73
US10740239B2Aug 11, 2020

Translation entry invalidation in a multithreaded data processing system

IBM3 citations73
US10725937B2Jul 28, 2020

Synchronized access to shared memory by extending protection for a store target address of a store-conditional request

IBM2 citations73
US10241945B2Mar 26, 2019

Memory move supporting speculative acquisition of source and destination data granules including copy-type and paste-type instructions

IBM3 citations73
US10042580B2Aug 7, 2018

Speculatively performing memory move requests with respect to a barrier

IBM3 citations73
US9928119B2Mar 27, 2018

Translation entry invalidation in a multithreaded data processing system

IBM3 citations73
US9792147B2Oct 17, 2017

Transactional storage accesses supporting differing priority levels

IBM4 citations73
US9715459B2Jul 25, 2017

Translation entry invalidation in a multithreaded data processing system

IBM5 citations73
US9696927B2Jul 4, 2017

Memory transaction having implicit ordering effects

IBM4 citations73
US9652399B2May 16, 2017

Expedited servicing of store operations in a data processing system

IBM5 citations73
US9645937B2May 9, 2017

Expedited servicing of store operations in a data processing system

IBM5 citations73
US9632943B2Apr 25, 2017

Expedited servicing of store operations in a data processing system

IBM5 citations73
US9514045B2Dec 6, 2016

Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system

IBM3 citations73
US9514083B1Dec 6, 2016

Topology specific replicated bus unit addressing in a data processing system

IBM3 citations73
US8806148B2Aug 12, 2014

Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration

IBM5 citations73
US11748267B1Sep 5, 2023

Concurrent processing of translation entry invalidation requests in a processor core

IBM2 citations72
US11163700B1Nov 2, 2021

Initiating interconnect operation without waiting on lower level cache directory lookup

IBM2 citations72
US10970215B1Apr 6, 2021

Cache snooping mode extending coherence protection for certain requests

IBM6 citations72

GUTHRIE GUY L

7 patents

ARIMILLI RAVI K

2 patents

CUMMINGS DAVID W

1 patent

Showing the top 50 of 202 patents by PatentIndex Score.