Inventor

WILLIAMS PHILLIP G

US47 patents

⚠️ This page may combine multiple inventors who share the name “WILLIAMS PHILLIP G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WILLIAMS PHILLIP G

IBM

Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit

System and method for supporting access to multiple I/O hub nodes in a host bridge

System and method for implementing private devices on a secondary peripheral component interface

Hybrid replacement policy in a multilevel cache memory hierarchy

Cache backing store for transactional memory

Data cache block deallocate requests in a multi-level cache hierarchy

Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memory

Empirically based dynamic control of transmission of victim cache lateral castouts

Data caching on bridge following disconnect

Adaptively enabling and disabling snooping bus commands

Virtual machine failover

Program counter (PC)-relative load and store addressing for fused instructions

Fusion to enhance early address generation of load instructions in a microprocessor

Adaptively enabling and disabling snooping fastpath commands

Virtual machines failover

Data cache block deallocate requests

Microprocessor that fuses load and compare instructions

Opaque memory region for I/O adapter transparent bridge

Program instruction scheduling

Operation of a multi-slice processor implementing datapath steering

Operation of a multi-slice processor implementing datapath steering

Adaptively enabling and disabling snooping bus commands

Preserving an invalid global domain indication when installing a shared cache line in a cache

Cache backing store for transactional memory

Techniques for preserving an invalid global domain indication when installing a shared cache line in a cache

Adaptively enabling and disabling snooping fastpath commands

Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor using null internal operations (IOPs)

Routing instructions in a microprocessor

Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor

Thread migration using a microcode engine of a multi-slice processor

Providing pseudo-randomized static values during LBIST transition tests

GUTHRIE GUY L

Lateral cache-to-cache cast-in

Lateral castout (LCO) of victim cache line in data-invalid state

Victim cache prefetching

Mode-based castout destination selection

Handling castout cache lines in a victim cache

Victim cache replacement

Bandwidth of a cache directory by slicing the cache directory into two smaller cache directories and replicating snooping logic for each sliced cache directory

Lateral castout target selection

Delete of cache line with correctable error

Processor, data processing system and method supporting a shared global coherency state

Formation of an exclusive ownership coherence state in a lower level cache upon replacement from an upper level cache of a cache line in a private shared owner state

GHAI SANJEEV

Data cache block deallocate requests

Data cache block deallocate requests in a multi-level cache hierarchy

GEN MOTORS CORP

Energy absorbing steering wheel assembly

CUMMINGS DAVID W

Updating partial cache lines in a data processing system

CLARK LEO JAMES

Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing