Inventor
LIBBY JEFFREY G
US38 patents
⚠️ This page may combine multiple inventors who share the name “LIBBY JEFFREY G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
JUNIPER NETWORKS INC
23 patentsUS7924860B1Apr 12, 2011
Maintaining data unit order in a network switching device
JUNIPER NETWORKS INC48 citations97
US6941433B1Sep 6, 2005
Systems and methods for memory read response latency detection
JUNIPER NETWORKS INC69 citations97
US7289503B1Oct 30, 2007
Systems and methods for efficient multicast handling
JUNIPER NETWORKS INC13 citations92
US7239630B1Jul 3, 2007
Dedicated processing resources for packet header generation
JUNIPER NETWORKS INC27 citations92
US7236501B1Jun 26, 2007
Systems and methods for handling packet fragmentation
JUNIPER NETWORKS INC24 citations92
US7215662B1May 8, 2007
Logical separation and accessing of descriptor memories
JUNIPER NETWORKS INC21 citations92
US7212530B1May 1, 2007
Optimized buffer loading for packet header processing
JUNIPER NETWORKS INC25 citations92
US7158520B1Jan 2, 2007
Mailbox registers for synchronizing header processing execution
JUNIPER NETWORKS INC21 citations92
US7916632B1Mar 29, 2011
Systems and methods for handling packet fragmentation
JUNIPER NETWORKS INC7 citations84
US7680116B1Mar 16, 2010
Optimized buffer loading for packet header processing
JUNIPER NETWORKS INC11 citations84
US7180893B1Feb 20, 2007
Parallel layer 2 and layer 3 processing components in a network router
JUNIPER NETWORKS INC19 citations84
US7859999B1Dec 28, 2010
Memory load balancing for single stream multicast
JUNIPER NETWORKS INC6 citations74
US7773599B1Aug 10, 2010
Packet fragment handling
JUNIPER NETWORKS INC6 citations74
US9880603B1Jan 30, 2018
Methods and apparatus for clock gating processing modules based on hierarchy and workload
JUNIPER NETWORKS INC4 citations72
US7936758B2May 3, 2011
Logical separation and accessing of descriptor memories
JUNIPER NETWORKS INC3 citations63
US7616562B1Nov 10, 2009
Systems and methods for handling packet fragmentation
JUNIPER NETWORKS INC3 citations62
US9116814B1Aug 25, 2015
Use of cache to reduce memory bandwidth pressure with processing pipeline
JUNIPER NETWORKS INC3 citations61
US9098262B2Aug 4, 2015
Efficient arithimetic logic units
JUNIPER NETWORKS INC0 citations52
US7782857B2Aug 24, 2010
Logical separation and accessing of descriptor memories
JUNIPER NETWORKS INC0 citations52
US10571988B1Feb 25, 2020
Methods and apparatus for clock gating processing modules based on hierarchy and workload
JUNIPER NETWORKS INC0 citations51
US7710994B1May 4, 2010
Systems and methods for efficient multicast handling
JUNIPER NETWORKS INC0 citations51
US9753524B1Sep 5, 2017
Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules
JUNIPER NETWORKS INC0 citations46
US9477257B1Oct 25, 2016
Methods and apparatus for limiting a number of current changes while clock gating to manage power consumption of processor modules
JUNIPER NETWORKS INC1 citations46
FRAILONG JEAN-MARC
4 patentsUS8069023B1Nov 29, 2011
Hardware support for instruction set emulation
FRAILONG JEAN-MARC91 citations97
US8520675B1Aug 27, 2013
System and method for efficient packet replication
FRAILONG JEAN-MARC16 citations83
US8880856B1Nov 4, 2014
Efficient arithmetic logic units
FRAILONG JEAN-MARC2 citations62
US8498306B2Jul 30, 2013
Maintaining data unit order in a network switching device
FRAILONG JEAN-MARC1 citations51
LIBBY JEFFREY G
3 patentsUS8078849B2Dec 13, 2011
Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table
LIBBY JEFFREY G8 citations82
US8799909B1Aug 5, 2014
System and method for independent synchronous and asynchronous transaction requests
LIBBY JEFFREY G6 citations71
US9026424B1May 5, 2015
Emulation of multiple instruction sets
LIBBY JEFFREY G2 citations61