Inventor
RIVERS JUDE A
US43 patents
⚠️ This page may combine multiple inventors who share the name “RIVERS JUDE A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
31 patentsUS9418721B2Aug 16, 2016
Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)
IBM52 citations98
US6678795B1Jan 13, 2004
Method and apparatus for memory prefetching based on intra-page usage history
IBM105 citations97
US9431084B2Aug 30, 2016
Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)
IBM34 citations94
US9351899B2May 31, 2016
Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)
IBM27 citations94
US7496733B2Feb 24, 2009
System and method of execution of register pointer instructions ahead of instruction issues
IBM38 citations92
US7454573B2Nov 18, 2008
Cost-conscious pre-emptive cache line displacement and relocation mechanisms
IBM25 citations92
US6948051B2Sep 20, 2005
Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width
IBM40 citations92
US6711651B1Mar 23, 2004
Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching
IBM39 citations92
US9116738B2Aug 25, 2015
Method and apparatus for efficient execution of concurrent processes on a multithreaded message passing system
IBM16 citations91
US7454316B2Nov 18, 2008
Method and apparatus for monitoring and enhancing on-chip microprocessor reliability
IBM35 citations91
US7366875B2Apr 29, 2008
Method and apparatus for an efficient multi-path trace cache design
IBM27 citations91
US7076681B2Jul 11, 2006
Processor with demand-driven clock throttling power reduction
IBM31 citations91
US9406368B2Aug 2, 2016
Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)
IBM5 citations84
US7472038B2Dec 30, 2008
Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques
IBM19 citations84
US9122513B2Sep 1, 2015
Method and apparatus for efficient execution of concurrent processes on a multithreaded message passing system
IBM7 citations82
US7506216B2Mar 17, 2009
System and method of workload-dependent reliability projection and monitoring for microprocessor chips and systems
IBM11 citations82
US7921331B2Apr 5, 2011
Write filter cache method and apparatus for protecting the microprocessor core from soft errors
IBM5 citations74
US7444544B2Oct 28, 2008
Write filter cache method and apparatus for protecting the microprocessor core from soft errors
IBM6 citations74
US9740496B2Aug 22, 2017
Processor with memory-embedded pipeline for table-driven computation
IBM2 citations73
US7340588B2Mar 4, 2008
Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
IBM5 citations73
US8796047B2Aug 5, 2014
Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip
IBM3 citations63
US7774654B2Aug 10, 2010
Method and apparatus for preventing soft error accumulation in register arrays
IBM4 citations63
US7552277B2Jun 23, 2009
Distributed buffer integrated cache memory organization and method for reducing energy consumption thereof
IBM2 citations63
US7493523B2Feb 17, 2009
Method and apparatus for preventing soft error accumulation in register arrays
IBM3 citations63
US7461209B2Dec 2, 2008
Transient cache storage with discard function for disposable data
IBM6 citations63
US7130963B2Oct 31, 2006
System and method for instruction memory storage and processing based on backwards branch control information
IBM5 citations63
US7865699B2Jan 4, 2011
Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
IBM2 citations62
US7325124B2Jan 29, 2008
System and method of execution of register pointer instructions ahead of instruction issue
IBM4 citations62
US7958334B2Jun 7, 2011
Method and apparatus for an efficient multi-path trace cache design
IBM1 citations61
US9740497B2Aug 22, 2017
Processor with memory-embedded pipeline for table-driven computation
IBM0 citations52
US7930525B2Apr 19, 2011
Method and apparatus for an efficient multi-path trace cache design
IBM0 citations51
BOSE PRADIP
5 patentsUS8679861B2Mar 25, 2014
Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip
BOSE PRADIP184 citations99
US8595731B2Nov 26, 2013
Low overhead dynamic thermal management in many-core cluster architecture
BOSE PRADIP12 citations84
US8091050B2Jan 3, 2012
Modeling system-level effects of soft errors
BOSE PRADIP7 citations84
US8108714B2Jan 31, 2012
Method and system for soft error recovery during processor execution
BOSE PRADIP0 citations52
US10216557B2Feb 26, 2019
Method and apparatus for monitoring and enhancing on-chip microprocessor reliability
BOSE PRADIP0 citations50