Inventor

SHAW THOMAS M

US74 patents

⚠️ This page may combine multiple inventors who share the name “SHAW THOMAS M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHAW THOMAS M

IBM

Process for producing metal interconnections and product produced thereby

Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures

Tuneable ferroelectric decoupling capacitor

Device and methodology for reducing effective dielectric constant in semiconductor devices

Electromigration resistant power distribution network

Via paste compositions and use thereof to form conductive vias in circuitized ceramic substrates

Hybrid interconnect structure for performance improvement and reliability enhancement

Device and methodology for reducing effective dielectric constant in semiconductor devices

Method for reducing film stress for SiCOH low-k dielectric materials

Crackstop with release layer for crack control in semiconductors

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor

Building metal pillars in a chip for structure support

Tuneable ferroelectric decoupling capacitor

Process for producing ceramic circuit structures having conductive vias

Stacked via-stud with improved reliability in copper metallurgy

Controlling fragmentation of chemically strengthened glass

Structure and method for making crack stop for 3D integrated circuits

Hybrid interconnect structure for performance improvement and reliability enhancement

Device and methodology for reducing effective dielectric constant in semiconductor devices

Hardmask for reliability of silicon based dielectrics

Process for interfacial adhesion in laminate structures through patterned roughing of a surface

Method of forming crack trapping and arrest in thin film structures

Method of extracting properties of back end of line (BEOL) chip architecture

Device and methodology for reducing effective dielectric constant in semiconductor devices

Building metal pillars in a chip for structure support

Integrated time dependent dielectric breakdown reliability testing

Controlling fragmentation of chemically strengthened glass

Piezoelectronic switch device for RF applications

Semiconductor article having a zig-zag guard ring and method of forming the same

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

Structure for determining thermal cycle reliability

Method and structure for determining thermal cycle reliability

Techniques to improve reliability in Cu interconnects using Cu intermetallics

Strain monitoring of MRAM arrays

Hybrid interconnect structure for performance improvement and reliability enhancement

Hybrid interconnect structure for performance improvement and reliability enhancement

Elastic modulus mapping of an integrated circuit chip in a chip/device package

Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same

Process for interfacial adhesion in laminate structures through patterned roughing of a surface

BEOL interconnect structures with improved resistance to stress

YANG CHIH-CHAO

Redundant metal barrier structure for interconnect applications

Redundant metal barrier structure for interconnect applications

Hybrid interconnect structure for performance improvement and reliability enhancement

EDELSTEIN DANIEL C

Reducing effective dielectric constant in semiconductor devices

LANE MICHAEL W

Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

FAROOQ MUKTA G

Structure and method for making crack stop for 3D integrated circuits

ROCKWELL INTERNATIONAL CORP

Mixing of ceramic powders

LINIGER ERIC G

Multiple step anneal method and semiconductor formed by multiple step anneal