Inventor

PACHAMUTHU JAYAVEL

US109 patents

⚠️ This page may combine multiple inventors who share the name “PACHAMUTHU JAYAVEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PACHAMUTHU JAYAVEL

SANDISK TECHNOLOGIES INC

Methods of fabricating a three-dimensional non-volatile memory device

High aspect ratio memory hole channel contact formation

Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation

Multilevel memory stack structure employing support pillar structures

Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks

Three dimensional NAND string memory devices with voids enclosed between control gate electrodes

Multilevel memory stack structure and methods of manufacturing the same

High dielectric constant etch stop layer for a memory structure

Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device

Methods of selective removal of blocking dielectric in NAND memory strings

Three dimensional NAND devices with air gap or low-k core

Methods of fabricating a three-dimensional non-volatile memory device

Method of making a vertical NAND device using sequential etching of multilayer stacks

Three dimensional memory device containing aluminum source contact via structure and method of making thereof

Three dimensional NAND device with channel contacting conductive source line and method of making thereof

Three-dimensional memory devices having a shaped epitaxial channel portion

Three-dimensional memory structure with multi-component contact via structure and method of making thereof

Multi-charge region memory cells for a vertical NAND device

Method of integrating select gate source and memory hole for three-dimensional non-volatile memory device

Method of making a vertical NAND device using sequential etching of multilayer stacks

Three-dimensional non-volatile memory device

Memory cell with high-k charge trapping layer

Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures

Method of making a three-dimensional memory array with etch stop

Three-dimensional memory device having a heterostructure quantum well channel

Three-dimensional memory structure having self-aligned drain regions and methods of making thereof

3D memory having crystalline silicon NAND string channel

Method of forming an active area with floating gate negative offset profile in FG NAND memory

Three-dimensional non-volatile memory device having a silicide source line and method of making thereof

Three dimensional memory device with hybrid source electrode for wafer warpage reduction

Vertical memory device with bit line air gap

Three dimensional NAND device with silicon germanium heterostructure channel

Three-dimensional integration schemes for reducing fluorine-induced electrical shorts

Three dimensional NAND device having reduced wafer bowing and method of making thereof

Metal replacement process for low resistance source contacts in 3D NAND

Techniques for detecting broken word lines in non-volatile memories

SANDISK TECHNOLOGIES LLC

Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof

Support pillar structures for leakage reduction in a three-dimensional memory device and methods of making the same

Support pillar structures for leakage reduction in a three-dimensional memory device

Multiple liner interconnects for three dimensional memory devices and method of making thereof

Offset backside contact via structures for a three-dimensional memory device

Erase stress and delta erase loop count methods for various fail modes in non-volatile memory

Inter-plane offset in backside contact via structures for a three-dimensional memory device

Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof

Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof

Three-dimensional memory device containing etch stop structures and methods of making the same

Select transistors with tight threshold voltage in 3D memory

PACHAMUTHU JAYAVEL

High aspect ratio memory hole channel contact formation

Air isolation in high density non-volatile memory

WESTERN DIGITAL TECH INC

Different word line programming orders in non-volatile memory for error recovery