Inventor
EICKEMEYER RICHARD JAMES
US31 patents
⚠️ This page may combine multiple inventors who share the name “EICKEMEYER RICHARD JAMES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
27 patentsUS6697935B1Feb 24, 2004
Method and apparatus for selecting thread switch events in a multithreaded processor
IBM273 citations99
US6694425B1Feb 17, 2004
Selective flush of shared and other pipeline stages in a multithread processor
IBM163 citations99
US6076157AJun 13, 2000
Method and apparatus to force a thread switch in a multithreaded processor
IBM292 citations99
US6988186B2Jan 17, 2006
Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry
IBM70 citations98
US6931639B1Aug 16, 2005
Method for implementing a variable-partitioned queue for simultaneous multithreaded processors
IBM115 citations98
US6567839B1May 20, 2003
Thread switch control in a multithreaded processor system
IBM424 citations98
US6105051AAug 15, 2000
Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
IBM148 citations98
US6061710AMay 9, 2000
Multithreaded processor incorporating a thread latch register for interrupt service new pending threads
IBM225 citations98
US5313634AMay 17, 1994
Computer system branch prediction of subroutine returns
IBM140 citations98
US6049867AApr 11, 2000
Method and system for multi-thread switching only when a cache miss occurs at a second or higher level
IBM110 citations95
US7877580B2Jan 25, 2011
Branch lookahead prefetch for microprocessors
IBM41 citations92
US7421567B2Sep 2, 2008
Using a modified value GPR to enhance lookahead prefetch
IBM18 citations92
US6021481AFeb 1, 2000
Effective-to-real address cache managing apparatus and method
IBM39 citations92
US5778208AJul 7, 1998
Flexible pipeline for interlock removal
IBM24 citations92
US5651136AJul 22, 1997
System and method for increasing cache efficiency through optimized data allocation
IBM91 citations92
US5940877AAug 17, 1999
Cache address generation with and without carry-in
IBM21 citations91
US7594096B2Sep 22, 2009
Load lookahead prefetch for microprocessors
IBM13 citations84
US10209995B2Feb 19, 2019
Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions
IBM5 citations73
US7444498B2Oct 28, 2008
Load lookahead prefetch for microprocessors
IBM6 citations73
US5652774AJul 29, 1997
Method and apparatus for decreasing the cycle times of a data processing system
IBM7 citations73
US6393552B1May 21, 2002
Method and system for dividing a computer processor register into sectors
IBM13 citations72
US6336160B1Jan 1, 2002
Method and system for dividing a computer processor register into sectors and storing frequently used values therein
IBM10 citations72
US8347068B2Jan 1, 2013
Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor
IBM2 citations63
US7620799B2Nov 17, 2009
Using a modified value GPR to enhance lookahead prefetch
IBM2 citations62
US7552318B2Jun 23, 2009
Branch lookahead prefetch for microprocessors
IBM3 citations62
US5802564ASep 1, 1998
Method and apparatus for increasing processor performance
IBM4 citations62
US5878243AMar 2, 1999
Apparatus for decreasing the cycle times of a data processing system
IBM1 citations52