Inventor
SOLECKI JEDRZEJ
PL9 patents
Patents
9 patentsUS9714981B2Jul 25, 2017
Test-per-clock based on dynamically-partitioned reconfigurable scan chains
MENTOR GRAPHICS CORP2 citations72
US9347993B2May 24, 2016
Test generation for test-per-clock
MENTOR GRAPHICS CORP3 citations72
US9335377B2May 10, 2016
Test-per-clock based on dynamically-partitioned reconfigurable scan chains
MENTOR GRAPHICS CORP3 citations72
US9003248B2Apr 7, 2015
Fault-driven scan chain configuration for test-per-clock
MENTOR GRAPHICS CORP6 citations72
US9933485B2Apr 3, 2018
Deterministic built-in self-test based on compressed test patterns stored on chip and their derivatives
MENTOR GRAPHICS CORP2 citations70
US10963612B2Mar 30, 2021
Scan cell architecture for improving test coverage and reducing test application time
MENTOR GRAPHICS CORP1 citations62
US10379161B2Aug 13, 2019
Scan chain stitching for test-per-clock
MENTOR GRAPHICS CORP1 citations62
US9009553B2Apr 14, 2015
Scan chain configuration for test-per-clock based on circuit topology
MENTOR GRAPHICS CORP1 citations51
US10509072B2Dec 17, 2019
Test application time reduction using capture-per-cycle test points
MENTOR GRAPHICS CORP0 citations38