Inventor

STEINMAN MAURICE B

US43 patents

⚠️ This page may combine multiple inventors who share the name “STEINMAN MAURICE B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STEINMAN MAURICE B

HEWLETT PACKARD DEVELOPMENT CO

Restoring access to a failed data storage device in a redundant memory system

Computer architecture and system for efficient management of bi-directional bus

System for minimizing memory bank conflicts in a computer system

Mechanism to reorder memory read and write transactions for reduced latency and increased bandwidth

Computer resource management and allocation system

Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

Mechanism to track all open pages in a DRAM memory system

Computer architecture and system for efficient management of bi-directional bus

Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

BRANOVER ALEXANDER

Method and apparatus for memory power management

Method and apparatus for cache control

Enhanced control of CPU parking and thread rescheduling for maximizing the benefits of low-power state

Power state management of an input/output servicing component of a processor system

Protocol for power state determination and demotion

Method and apparatus for transitioning devices between power states based on activity request frequency

North-bridge to south-bridge protocol for placing processor in low power state

Managing processor-state transitions

Cache flush based on idle prediction and probe activity level

ADVANCED MICRO DEVICES INC

Method and apparatus for cache control

Integrating display controller into low power processor

Mechanism for throttling untrusted interconnect agents

Method for adaptive performance optimization of the soc

Mechanism for throttling untrusted interconnect agents

Distributed coherence directory subsystem with exclusive data regions

Distributed coherence directory subsystem with exclusive data regions

Dynamic performance control of processing nodes

Mechanism for resource utilization metering in a computer system

INTEL CORP

Methods and apparatuses to effect a variable-width link

Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link

Deterministic operation of an input/output interface

Methods and apparatuses for detecting clock failure and establishing an alternate clock lane

DIGITAL EQUIPMENT CORP

Write back buffer with error correcting capabilities

Method and apparatus for updating a duplicate tag status in a snoop bus protocol based computer system

Turbotable: apparatus for directing address and commands between multiple consumers on a node coupled to a pipelined system bus

STEINMAN MAURICE B

Method for SOC performance and power optimization

Processor bridge power management

KRISHNAN GUHAN

Hierarchical memory arbitration technique for disparate sources

Hierarchical memory arbitration technique for disparate sources

ATI TECHNOLOGIES ULC

Alternative protocol over physical layer

Alternative protocol over physical layer

COMPAQ INFORMATION TECHNOLOGIE

Proprammable DRAM address mapping mechanism

BRANOVER ALEXANDER J

Method and apparatus for transitioning a system to an active disconnect state

SADOWSKI GREG

Adaptive connected standby for a computing device