Inventor

KALAMATIANOS JOHN

US91 patents

⚠️ This page may combine multiple inventors who share the name “KALAMATIANOS JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KALAMATIANOS JOHN

ADVANCED MICRO DEVICES INC

Detecting and correcting hard errors in a memory array

Preserving memory ordering between offloaded instructions and non-offloaded instructions

Processor-guided execution of offloaded instructions using fixed function operations

Method and apparatus for virtualizing the micro-op cache

Method and apparatus for cache control

Method and apparatus for a page-local delta-based prefetcher

Management of cache size

Branch target filtering based on memory region access count

Method and apparatus for virtualizing the micro-op cache

Processor-guided execution of offloaded instructions using fixed function operations

Approach for managing near-memory processing commands and non-near-memory processing commands in a memory controller

Energy efficient adaptive data encoding method and circuit

Implementing a micro-operation cache with compaction

System and method for protecting GPU memory instructions against faults

System and method for protecting GPU memory instructions against faults

Flexible dictionary sharing for compressed caches

Semi-sorting compression with encoding and decoding tables

Flexible dictionary sharing for compressed caches

Compressing tags in software and hardware semi-sorted caches

Tracking prefetcher accuracy and coverage

Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host

Zero operand instruction conversion for accelerating sparse computations in a central processing unit pipeline

Offloading computations from a processor to remote execution logic

Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers

Method and apparatus for using compression to improve performance of low voltage caches

Per-instruction energy debugging using instruction sampling hardware

Dynamic evaluation and reconfiguration of a data prefetcher

Energy efficient adaptive data encoding method and circuit

Storing indications of cleared cache lines

Preserving memory ordering between offloaded instructions and non-offloaded instructions

Modifying system directory capacity based on power state transition

Systems and methods for branch misprediction aware cache prefetcher training

Implementing a micro-operation cache with compaction

Accessing a cache based on an address translation buffer result

Speculative dram request enabling and disabling

Flexible dictionary sharing for compressed caches

DRAM row management for processing in memory

Method and apparatus for reducing the latency of long latency memory requests

Error detection and correction in memory modules using programmable ECC engines

Approach for supporting memory-centric operations on cached data

Controlling the operating speed of stages of an asynchronous pipeline

Semi-sorting compression with encoding and decoding tables

System and method for protecting GPU memory instructions against faults

Method and apparatus to support instruction replay for executing idempotent code in dependent processing in memory devices

NUSSBAUM SEBASTIEN

Altering performance of computational units heterogeneously according to performance sensitivity

Throttling computational units according to performance sensitivity

BRANOVER ALEXANDER

Method and apparatus for cache control

SADOWSKI GREG

Energy efficient adaptive data encoding method and circuit

KRISHNAN GUHAN

Hierarchical memory arbitration technique for disparate sources

KALAMATIANOS JOHN

Prefetching to a cache based on buffer fullness