Inventor
STEINMETZ JOSEPH H
US19 patents
⚠️ This page may combine multiple inventors who share the name “STEINMETZ JOSEPH H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICRON TECHNOLOGY INC
8 patentsUS11775368B2Oct 3, 2023
Node coherency for storage related data
MICRON TECHNOLOGY INC2 citations73
US11429544B2Aug 30, 2022
Enabling devices with enhanced persistent memory region access
MICRON TECHNOLOGY INC3 citations73
US12118220B2Oct 15, 2024
Elastic persistent memory regions
MICRON TECHNOLOGY INC0 citations62
US12086468B2Sep 10, 2024
Split protocol approaches for enabling devices with enhanced persistent memory region access
MICRON TECHNOLOGY INC0 citations62
US12045118B2Jul 23, 2024
Node coherency for storage related data
MICRON TECHNOLOGY INC0 citations62
US11704029B2Jul 18, 2023
Elastic persistent memory regions
MICRON TECHNOLOGY INC0 citations62
US11704060B2Jul 18, 2023
Split protocol approaches for enabling devices with enhanced persistent memory region access
MICRON TECHNOLOGY INC0 citations62
US11693797B2Jul 4, 2023
Enabling devices with enhanced persistent memory region access
MICRON TECHNOLOGY INC0 citations62
AGILENT TECHNOLOGIES INC
5 patentsUS6425034B1Jul 23, 2002
Fibre channel controller having both inbound and outbound control units for simultaneously processing both multiple inbound and outbound sequences
AGILENT TECHNOLOGIES INC93 citations96
US6314477B1Nov 6, 2001
Performance of fibre channel protocol sequence reassembly using expected frame information and buffer list calculations
AGILENT TECHNOLOGIES INC79 citations93
US6336157B1Jan 1, 2002
Deterministic error notification and event reordering mechanism provide a host processor to access complete state information of an interface controller for efficient error recovery
AGILENT TECHNOLOGIES INC24 citations87
US6578096B1Jun 10, 2003
Method and system for efficient I/O operation completion in a fibre channel node
AGILENT TECHNOLOGIES INC17 citations83
US6526458B1Feb 25, 2003
Method and system for efficient i/o operation completion in a fibre channel node using an application specific integration circuit and determining i/o operation completion status within interface controller
AGILENT TECHNOLOGIES INC12 citations69
HEWLETT PACKARD CO
3 patentsUS5809521ASep 15, 1998
Single and multistage stage fifo designs for data transfer synchronizers
HEWLETT PACKARD CO20 citations91
US6208703B1Mar 27, 2001
First-in-first-out synchronizer
HEWLETT PACKARD CO24 citations86
US6055588AApr 25, 2000
Single stage FIFO memory with a circuit enabling memory to be read from and written to during a single cycle from a single clock
HEWLETT PACKARD CO9 citations72
STEINMETZ JOSEPH H
2 patentsUS8321650B2Nov 27, 2012
Alignment-unit-based virtual formatting methods and devices employing the methods
STEINMETZ JOSEPH H20 citations89
US8095704B2Jan 10, 2012
Integrated-circuit implementation of a storage-shelf router and a path controller card for combined use in high-availability mass-storage-device shelves that may be incorporated within disk arrays
STEINMETZ JOSEPH H0 citations36