Inventor
COLLURA ADAM B
US38 patents
⚠️ This page may combine multiple inventors who share the name “COLLURA ADAM B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
30 patentsUS9606805B1Mar 28, 2017
Accuracy of operand store compare prediction using confidence counter
IBM7 citations84
US9495156B1Nov 15, 2016
Accuracy of operand store compare prediction using confidence counter
IBM6 citations84
US9471314B1Oct 18, 2016
Auxiliary perceptron branch predictor with magnitude usage limit
IBM13 citations84
US9442726B1Sep 13, 2016
Perceptron branch predictor with virtualized weights
IBM13 citations84
US10754781B2Aug 25, 2020
Heuristic method to control fetching of metadata from a cache hierarchy
IBM2 citations73
US10423419B2Sep 24, 2019
Stream based branch prediction index accelerator for multiple stream exits
IBM2 citations73
US10423420B2Sep 24, 2019
Stream based branch prediction index accelerator for multiple stream exits
IBM2 citations73
US10394559B2Aug 27, 2019
Branch predictor search qualification using stream length prediction
IBM3 citations73
US10175893B2Jan 8, 2019
Predictive scheduler for memory rank switching
IBM2 citations73
US9934040B2Apr 3, 2018
Perceptron branch predictor with virtualized weights
IBM4 citations73
US9594566B1Mar 14, 2017
Accuracy of operand store compare prediction using confidence counter
IBM4 citations73
US9543963B2Jan 10, 2017
Modulo-m binary counter
IBM5 citations73
US9298619B2Mar 29, 2016
Cache line history tracking using an instruction address register file storing memory location identifier
IBM3 citations73
US10430195B2Oct 1, 2019
Stream based branch prediction index accelerator with power prediction
IBM1 citations62
US10379748B2Aug 13, 2019
Predictive scheduler for memory rank switching
IBM1 citations62
US10908902B2Feb 2, 2021
Distance based branch prediction and detection of potential call and potential return instructions
IBM0 citations52
US10437597B2Oct 8, 2019
Silent mode and resource reassignment in branch prediction logic
IBM0 citations52
US9904554B2Feb 27, 2018
Checkpoints for a simultaneous multithreading processor
IBM0 citations52
US9792124B2Oct 17, 2017
Speculative branch handling for transaction abort
IBM0 citations52
US9720694B2Aug 1, 2017
Silent mode and resource reassignment in branch prediction logic for branch instructions within a millicode routine
IBM0 citations52
US9672045B2Jun 6, 2017
Checkpoints for a simultaneous multithreading processor
IBM0 citations52
US9619237B2Apr 11, 2017
Speculative branch handling for transaction abort
IBM0 citations52
US9606927B2Mar 28, 2017
Set selection of a set-associative storage container
IBM0 citations52
US9582425B2Feb 28, 2017
Set selection of a set-associative storage container
IBM0 citations52
US9495300B2Nov 15, 2016
Set selection of a set-associative storage container
IBM0 citations52
US9454377B2Sep 27, 2016
Speculative branch handling for transaction abort
IBM0 citations52
US9424044B1Aug 23, 2016
Silent mode and resource reassignment in branch prediction logic for branch instructions within a millicode routine
IBM0 citations52
US9135013B2Sep 15, 2015
Instruction filtering
IBM0 citations52
US9128759B2Sep 8, 2015
Decimal multi-precision overflow and tininess detection
IBM0 citations51
US11175923B2Nov 16, 2021
Comparing load instruction address fields to store instruction address fields in a table to delay issuing dependent load instructions
IBM0 citations50
CARLOUGH STEVEN R
4 patentsUS8554822B2Oct 8, 2013
Decimal adder with end around carry
CARLOUGH STEVEN R6 citations72
US8495124B2Jul 23, 2013
Decimal floating point mechanism and process of multiplication without resultant leading zero detection
CARLOUGH STEVEN R2 citations63
US8443227B2May 14, 2013
Processor and method for workaround trigger activated exceptions
CARLOUGH STEVEN R4 citations62
US8572141B2Oct 29, 2013
Execution of fixed point instructions using a decimal floating point unit
CARLOUGH STEVEN R4 citations61
COLLURA ADAM B
3 patentsUS9213641B2Dec 15, 2015
Cache line history tracking using an instruction address register file
COLLURA ADAM B2 citations61
US8495287B2Jul 23, 2013
Clock-based debugging for embedded dynamic random access memory element in a processor core
COLLURA ADAM B4 citations60
US8392490B2Mar 5, 2013
Identifying decimal floating point addition operations that do not require alignment, normalization or rounding
COLLURA ADAM B0 citations38