Inventor

CARLOUGH STEVEN R

US152 patents

⚠️ This page may combine multiple inventors who share the name “CARLOUGH STEVEN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CARLOUGH STEVEN R

IBM

System and method for converting from scaled binary coded decimal into decimal floating point

System and method for providing a decimal multiply algorithm using a double adder

Storage pre-alignment and EBCDIC, ASCII and unicode basic latin conversions for packed decimal data

Process of operations with an interchangeable transmission device and apparatus for use therein for a common interface for use with digital cameras

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Variable acknowledge rate to reduce bus contention in presence of communication errors

System and method for performing decimal floating point addition

Decimal multiplication using digit recoding

Multi-pipe dispatch and execution of complex instructions in a superscalar processor

Inference based condition code generation

Modular binary multiplier for signed and unsigned operands of variable widths

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Residue prediction of packed data

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Decimal floating point instructions to perform directly on compressed decimal floating point data

Decimal shift and divide instruction

Partial data replay in a distributed memory buffer system

Modulo-m binary counter

Confidence threshold-based opposing branch path execution for branch prediction

Confidence threshold-based opposing branch path execution for branch prediction

Thread sparing between cores in a multi-threaded processor

Modular binary multiplier for signed and unsigned operands of variable widths

Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection

Inference based condition code generation

Inference based condition code generation

Speculative bank activate dynamic random access memory (DRAM) scheduler

Speculative bank activate dynamic random access memory (DRAM) scheduler

Reproducible stochastic rounding for out of order processors

Management of resources within a computing environment

Convert from zoned format to decimal floating point format

Hardware recovery in multi-threaded processor

In situ processor re-characterization

Management of resources within a computing environment

Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors

System and method for performing decimal to binary conversion

Decimal multiplication for superscaler processors

Decimal multiplication for superscaler processors

BUSABA FADI Y

Hardware recovery in multi-threaded processor

Reconfigurable recovery modes in high availability processors

Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors

Variable acknowledge rate to reduce bus contention in presence of communication errors

In situ processor re-characterization

Management of resources within a computing environment

Cache set replacement order based on temporal set recording

CARLOUGH STEVEN R

Convert from zoned format to decimal floating point format

Convert to zoned format from decimal floating point format

Range check based lookup tables

Decimal adder with end around carry

Decimal floating point mechanism and process of multiplication without resultant leading zero detection