Inventor

SCHWARZ ERIC M

US236 patents

⚠️ This page may combine multiple inventors who share the name “SCHWARZ ERIC M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHWARZ ERIC M

IBM

Generalized 7/3 counters

Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures

Composition of decimal floating point data

Shift significand of decimal floating point data

Dynamic predictor for coalescing memory transactions

Instruction to cancel outstanding cache prefetches

Transaction tracking within a microprocessor

Vector checksum instruction

Vector checksum instruction

Prefetching of discontiguous storage locations in anticipation of transactional execution

Modify and execute sequential instruction facility and instructions therefor

Salvaging hardware transactions

Dynamic predictor for coalescing memory transactions

Decomposition of decimal floating point data

Round for reround mode in a decimal floating point instruction

Checksum adder

System and method for converting from scaled binary coded decimal into decimal floating point

System and method for providing a decimal multiply algorithm using a double adder

Two&#39;s complement multiplication with a sign magnitude multiplier

Round for reround mode in a decimal floating point instruction

Prioritization of transactions based on execution by transactional core with super core indicator

Hardware transaction transient conflict resolution

Transactional memory operations with read-only atomicity

Shift significand of decimal floating point data

Floating point instruction with selectable comparison attributes

Multi-granular cache management in multi-processor computing environments

Speculation control for improving transaction success rate, and instruction therefor

Salvaging hardware transactions with instructions

Supporting atomic accumulation with an addressable accumulator

Multithreaded transactions

Multithreaded transactions

Instruction to load data up to a specified memory boundary indicated by the instruction

Prefetching of discontiguous storage locations as part of transactional execution

Salvaging hardware transactions with instructions

Salvaging hardware transactions

Salvaging hardware transactions

Salvaging hardware transactions with instructions

Salvaging hardware transactions

Round for reround mode in a decimal floating point instruction

Centralized management of high-contention cache lines in multi-processor computing environments

Emulating hexadecimal floating-point operations in non-native systems

System and method for a floating point unit with feedback prior to normalization and rounding

LUNDVALL SHAWN D

Composition of decimal floating point data

Employing a mask field of an instruction to encode a sign of a result of the instruction

Composition of decimal floating point data, and methods therefor

Decomposition of decimal floating point data, and methods therefor

Shift significand of decimal floating point data

Convert significand of decimal floating point data from packed decimal format

GLOBALFOUNDRIES INC

Managing high-conflict cache lines in transactional memory computing environments

CARLOUGH STEVEN R

Convert from zoned format to decimal floating point format

Two's complement multiplication with a sign magnitude multiplier