Inventor

HUANG ELBERT E

US70 patents

⚠️ This page may combine multiple inventors who share the name “HUANG ELBERT E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG ELBERT E

IBM

Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer

Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect

Interconnect structures with fully aligned vias

Air gap semiconductor structure with selective cap bilayer

Device and methodology for reducing effective dielectric constant in semiconductor devices

Selective and non-selective barrier layer wet removal

Interconnect structure having subtractive etch feature and damascene feature

Device and methodology for reducing effective dielectric constant in semiconductor devices

Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence

Patterning layers comprised of spin-on ceramic films

MOSFET structure with ultra-low K spacer

Interconnect structure having subtractive etch feature and damascene feature

Selective and non-selective barrier layer wet removal

Interconnect structures with fully aligned vias

Interconnect structure having substractive etch feature and damascene feature

Selective and non-selective barrier layer wet removal

Electromigration test structure for Cu barrier integrity and blech effect evaluations

Vertical electronic fuse

Sealed air gap for semiconductor chip

Device and methodology for reducing effective dielectric constant in semiconductor devices

Temporary etchable liner for forming air gap

Sub-lithographic dimensioned air gap formation and related structure

Antireflective composition and process of making a lithographic structure

Multilayered cap barrier in microelectronic interconnect structures

Method of forming an air gap semiconductor structure with selective cap bilayer

Anisotropic stress generation by stress-generating liners having a sublithographic width

Device and methodology for reducing effective dielectric constant in semiconductor devices

Method of fabricating a multilayered dielectric diffusion barrier layer

Method of forming a ceramic diffusion barrier layer

Polycarbosilane buried etch stops in interconnect structures

Interconnect structures incorporating low-k dielectric barrier films

Patterning layers comprised of spin-on ceramic films

Selective recessing to form a fully aligned via

Low aspect ratio interconnect

Interconnect structures with fully aligned vias

Barrier planarization for interconnect metallization

Air gap semiconductor structure with selective cap bilayer

Corrugated interfaces for multilayered interconnects

Corrugated interfaces for multilayered interconnects

EDELSTEIN DANIEL C

Microelectronic structure including air gap

Reducing effective dielectric constant in semiconductor devices

Microelectronic structure including air gap

Structure with self aligned resist layer on an interconnect surface and method of making same

Structure with self aligned resist layer on an interconnect surface and method of making same

Microelectronic structure including air gap

HORAK DAVID V

Sealed air gap for semiconductor chip

BREYTA GREGORY

Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approach

GLOBALFOUNDRIES INC

Alternate dual damascene method for forming interconnects

PONOTH SHOM

Structure for nano-scale metallization and method for fabricating same

BONILLA GRISELDA

Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer