Inventor
MANEPALLI RAHUL
US28 patents
⚠️ This page may combine multiple inventors who share the name “MANEPALLI RAHUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
26 patentsUS7202304B2Apr 10, 2007
Anhydride polymers for use as curing agents in epoxy resin-based underfill material
INTEL CORP19 citations92
US7041736B2May 9, 2006
Anhydride polymers for use as curing agents in epoxy resin-based underfill material
INTEL CORP22 citations92
US6620512B2Sep 16, 2003
Anhydride polymers for use as curing agents in epoxy resin-based underfill material
INTEL CORP23 citations92
US6794225B2Sep 21, 2004
Surface treatment for microelectronic device substrate
INTEL CORP19 citations91
US11355438B2Jun 7, 2022
Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications
INTEL CORP6 citations86
US11990427B2May 21, 2024
Chiplet first architecture for die tiling applications
INTEL CORP2 citations73
US11973041B2Apr 30, 2024
Chiplet first architecture for die tiling applications
INTEL CORP2 citations73
US11769735B2Sep 26, 2023
Chiplet first architecture for die tiling applications
INTEL CORP1 citations73
US12308329B2May 20, 2025
Chiplet first architecture for die tiling applications
INTEL CORP0 citations62
US12243825B2Mar 4, 2025
Hybrid conductive vias for electronic substrates
INTEL CORP0 citations62
US12125793B2Oct 22, 2024
Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications
INTEL CORP0 citations62
US12087695B2Sep 10, 2024
Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications
INTEL CORP0 citations62
US11978685B2May 7, 2024
Glass core patch with in situ fabricated fan-out layer to enable die tiling applications
INTEL CORP1 citations62
US11756890B2Sep 12, 2023
Hybrid fan-out architecture with EMIB and glass core for heterogeneous die integration applications
INTEL CORP0 citations62
US11658055B2May 23, 2023
Customizable release layers to enable low warpage architectures for advanced packaging applications
INTEL CORP0 citations62
US12568831B2Mar 3, 2026
Patternable die attach materials and processes for patterning
INTEL CORP0 citations61
US11923312B2Mar 5, 2024
Patternable die attach materials and processes for patterning
INTEL CORP0 citations61
US11694898B2Jul 4, 2023
Hybrid fine line spacing architecture for bump pitch scaling
INTEL CORP0 citations61
US11445616B2Sep 13, 2022
Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures
INTEL CORP0 citations61
US11177234B2Nov 16, 2021
Package architecture with improved via drill process and method for forming such package
INTEL CORP0 citations61
US12341117B2Jun 24, 2025
Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates
INTEL CORP0 citations60
US12159825B2Dec 3, 2024
Dielectric-to-metal adhesion promotion material
INTEL CORP0 citations60
US8377550B2Feb 19, 2013
Flip chip package containing novel underfill materials
INTEL CORP2 citations59
US11646274B2May 9, 2023
Multi-package assemblies having foam structures for warpage control
INTEL CORP0 citations58
US11501967B2Nov 15, 2022
Selective metal deposition by patterning direct electroless metal plating
INTEL CORP0 citations49
US12416093B2Sep 16, 2025
Electroless plating process
INTEL CORP0 citations43
XU DINGYING
2 patentsUS8287996B2Oct 16, 2012
Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die
XU DINGYING5 citations71
US8569108B2Oct 29, 2013
Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die
XU DINGYING0 citations50