Inventor

BARTOLI SIMONE

IT45 patents

⚠️ This page may combine multiple inventors who share the name “BARTOLI SIMONE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARTOLI SIMONE

ATMEL CORP

Variable charge pump circuit with dynamic load

Flash memory architecture with page mode erase using NMOS and PMOS row decoding scheme

Erase verify method for NAND-type flash memories

System for performing fast testing during flash reference cell setting

System for configuring parameters for a flash memory

Method and system for configuring parameters for flash memory

Non-volatile memory array architecture with joined word lines

Compensated current offset in a sensing circuit

DAC-based voltage regulator for flash memory array

Method and system for regulating a program voltage value during multilevel memory device programming

Method and system for managing a suspend request in a flash memory

System and method for matching resistance in a non-volatile memory

Flexible, low cost apparatus and method to introduce and check algorithm modifications in a non-volatile memory

Method and system for reducing soft-writing in a multi-level flash memory

Method and system for regulating a program voltage value during multilevel memory device programming

Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device

Sense amplifier

Method and apparatus for discharging a memory cell in a memory device after an erase operation

Implementation of column redundancy for a flash memory with a high write parallelism

Method and system for a programming approach for a nonvolatile electronic device

Column decoding architecture for flash memories

Sense architecture

Method and system for managing address bits during buffered program operations in a memory device

ST MICROELECTRONICS SRL

Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration

Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read

Non-volatile memory with a charge pump with regulated voltage

Architecture for handling internal voltages in a non-volatile memory, particularly in a single-voltage supply type of dual-work flash memory

Sectored semiconductor memory device with configurable memory sector addresses

Method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor non-volatile storage device

Non-volatile memory device with burst mode reading and corresponding reading method

Pulse generator independent of supply voltage

Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit

Semiconductor device with selectable pads

Buffer device with dual supply voltage for low supply voltage applications

Autotesting method of a memory cell matrix, particularly of the non-volatile type

SGS THOMSON MICROELECTRONICS

Device for generating and regulating a gate voltage in a non-volatile memory

Supply voltages switch circuit

CMOS twin-tub negative voltage switching architecture

STMICROELCTRONICS S R L

Threshold voltage reduction of a transistor connected as a diode

KHOURI OSAMA

Method of programming selection transistors for NAND flash memory

PASSERINI MARCO

Method and circuit to discharge bit lines after an erase pulse

MICROCHIP TECH INC

Memory device, memory address decoder, system, and related method for memory attack detection

FERRAGINA VINCENZO

Erase techniques and circuits therefor for non-volatile memory devices

BARTOLI SIMONE

Memory device in particular extra array configured therein for configuration and redundancy information

PS4 LUXCO SARL

Erase techniques and circuits therefor for non-volatile memory devices