Inventor

DEBROSSE JOHN K

US73 patents

⚠️ This page may combine multiple inventors who share the name “DEBROSSE JOHN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DEBROSSE JOHN K

IBM

MRAM array having a segmented bit line

Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory

Error detection and correction method and apparatus in a magnetoresistive random access memory

Four F-squared gapless dual layer bitline DRAM array architecture

SOI DRAM with field-shield isolation and body contact

Self-aligned buried strap for trench type DRAM cells

Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices

Method of making buried strap trench cell yielding an extended transistor

Single twist layout and method for paired line conductors of integrated circuits

Method for providing silicide bridge contact between silicon regions separated by a thin dielectric

High density planar magnetic domain wall memory apparatus

Method of forming high density planar magnetic domain wall memory

Planarized and fill biased integrated circuit chip

Floating bitline timer allowing a shared equalizer DRAM sense amplifier

Integrated circuit planarization and fill biasing design method

Method and apparatus for redundancy word line replacement in a repairable semiconductor memory device

DRAM signal margin test method

Method of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack level

SOI DRAM with field-shield isolation

Apparatus and method for implementing precise sensing of PCRAM devices

Method and apparatus for current sense amplifier calibration in MRAM devices

Cascode complimentary dual level shifter

STT MRAM source line configuration

STT MRAM common source line array bias scheme

Nonvolatile memory interface for metadata shadowing

Spin torque transfer MRAM device formed on silicon stud grown by selective epitaxy

Mismatch and noise insensitive sense amplifier circuit for STT MRAM

Memory array with self-aligned epitaxially grown memory elements and annular FET

High density planar magnetic domain wall memory apparatus

Design structure for initializing reference cells of a toggle switched MRAM device

Method and structure for selecting anisotropy axis angle of MRAM device for reduced power consumption

Reduced bit line equalization level sensing scheme

Buried strap trench cell yielding an extended transistor

Dynamic random access memory with a simple test arrangement

Magnetic tunnel junction based anti-fuses with cascoded transistors

Three terminal spin hall MRAM

Bit line clamp voltage generator for STT MRAM sensing

STT MRAM midpoint reference cell allowing full write

Bit line clamp voltage generator for STT MRAM sensing

Mismatch and noise insensitive sense amplifier circuit for STT MRAM

Magnetic tunnel junction based anti-fuses with cascoded transistors

Spin torque transfer MRAM device formed on silicon stud grown by selective epitaxy

Mismatch and noise insensitive sense amplifier circuit for STT MRAM

Read circuit for memory

Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns

DEBROSSE JOHN K

Spin-torque transfer magneto-resistive memory architecture

Array architecture and operation for high density magnetic racetrack memory system

TOSHIBA KK

Exchangeable hierarchical data line structure

GLOBALFOUNDRIES INC

Offset-cancelling self-reference STT-MRAM sense amplifier

INFINEON TECHNOLOGIES AG

Circuit configuration for a current switch of a bit/word line of a MRAM device