Inventor

FRANCESCHINI MICHELE M

US89 patents

⚠️ This page may combine multiple inventors who share the name “FRANCESCHINI MICHELE M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FRANCESCHINI MICHELE M

IBM

Iterative write pausing techniques to improve read latency of memory systems

Adaptive wear leveling via monitoring the properties of memory reference stream

Memory reading method for resistance drift mitigation

Automatically linking text to concepts in a knowledge base

Automatic new concept definition

Automatically linking text to concepts in a knowledge base

Automatically linking text to concepts in a knowledge base

Computing the relevance of a document to concepts not specified in the document

Inverted table for storing and querying conceptual indices

User interface for summarizing the relevance of a document to a query

Computing the relevance of a document to concepts not specified in the document

Inverted table for storing and querying conceptual indices

Matrix ordering for cache efficiency in performing large sparse matrix operations

User interface for summarizing the relevance of a document to a query

Nonvolatile memory interface for metadata shadowing

DRAM error detection, evaluation, and correction

DRAM error detection, evaluation, and correction

Iteratively writing contents to memory locations using a statistical model

Coding techniques for improving the sense margin in content addressable memories

Estimation of closeness of topics based on graph analytics

Estimation of closeness of topics based on graph analytics

System for searching, recommending, and exploring documents through conceptual associations

Automatic new concept definition

System for searching, recommending, and exploring documents through conceptual associations

Automatically linking text to concepts in a knowledge base

Concept analysis operations utilizing accelerators

Securing the contents of a memory device

Encoding data into constrained memory

Artificial intelligence software marketplace

Hybrid storage system employing reconfigurable memory

Securing the contents of a memory device

Managing errors in a DRAM by weak cell encoding

FRANCESCHINI MICHELE M

Adaptive endurance coding of non-volatile memories

Multi-write endurance and error control coding of non-volatile memories

Wear-focusing of non-volatile memories for improved endurance

Solid-state storage management

Memory cell presetting for improved memory performance

Method for optimizing refresh rate for DRAM

Accessing coded data stored in a non-volatile memory

Probabilistic multi-tier error correction in not-and (NAND) flash memory

Multi-write coding of non-volatile memories

Non-volatile memories with enhanced write performance and endurance

Memory reading method for resistance drift mitigation

DRAM refresh

GLOBALFOUNDRIES INC

Implementing reinforcement learning based flash control

Local direct storage class memory access

BREITWISCH MATTHEW J

Resistive memory devices having a not-and (NAND) structure

BIVENS JOHN A

Bad block management for flash memory

ELFADEL IBRAHIM M

Adjustable write bins for multi-level analog memories

DODSON JOHN S

Isolation of faulty links in a transmission medium