Inventor

MOMTAZ AFSHIN

US105 patents

⚠️ This page may combine multiple inventors who share the name “MOMTAZ AFSHIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOMTAZ AFSHIN

BROADCOM CORP

Threshold adjust system and method

Phase adjust using relative error

Transceiver including a high latency communication channel and a low latency communication channel

System and method for adjusting multiple control loops using common criteria

Methods and circuitry for implementing first-in first-out structure

Integrated decision feedback equalizer and clock and data recovery

Built-in self-test for multi-channel transceivers without data alignment

Varactor based differential VCO band switching

High speed receive equalizer architecture

Continuous time filter-decision feedback equalizer architecture for optical channel equalization

Digitally adjustable variable gain amplifier (VGA) using switchable differential pairs

Resistor compensation apparatus

VGA-CTF combination cell for 10 Gb/s serial data receivers

GM cell based control loops

Gain control for interleaved analog-to-digital conversion for electronic dispersion compensation

Transceiver including a high latency communication channel and a low latency communication channel

High speed receive equalizer architecture

Low power high-speed output driver

Apparatus and method for analog-to-digital converter calibration

Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer

Transition insensitive timing recovery method and apparatus

Configurable voltage controlled oscillator system and method

High-speed, low-power reconfigurable voltage-mode DAC-driver

Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery

Decision feedback equalizer circuit

Search engine for a receive equalizer

Automatic gain control using multi-comparators

High speed peak amplitude comparator

Phase control for interleaved analog-to-digital conversion for electronic dispersion compensation

Transceiver system and method supporting variable rates and multiple protocols

Low-power high swing CML driver with independent common-mode and swing control

GM cell based control loops

Apparatus and method for analog-to-digital converter calibration

Fully differential CMOS phase-locked loop

Methods and circuitry for implementing first-in first-out structure

Methods and circuitry for implementing first-in first-out structure

Phase-locked loop circuit

Fast acquisition phase locked loop using a current DAC

Methods and circuitry for implementing first-in first-out structure

CMOS lock detect with double protection

Fully differential CMOS phase-locked loop

Stable phase locked loop having separated pole

Increasing output amplitude of a voltage-mode driver in a low supply voltage technology

Digitally adjusted variable gain amplifier (VGA) using switchable differential pairs

RAGHAVAN BHARATH

Resonant clock amplifier with a digitally tunable delay

Summer block for a decision feedback equalizer

NEWPORT COMMUNICATIONS INC

Stable phase locked loop having separated pole

AVAGO TECHNOLOGIES GENERAL IP

Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration

CUI DELONG

Amplifier bandwidth extension for high-speed tranceivers

AVAGO TECH INT SALES PTE LID

Integrated transimpedance amplifier with a digital signal processor for high-speed optical receivers