Inventor

BAUMAN MITCHELL A

US47 patents

⚠️ This page may combine multiple inventors who share the name “BAUMAN MITCHELL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAUMAN MITCHELL A

UNISYS CORP

High-performance modular memory system with crossbar connections

High-performance modular memory system with crossbar connections

High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems

Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues

System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module

System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency

Scalable cross bar type storage controller

System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching scheme

Programmable address translation system

System and method for bypassing supervisory memory intervention for data transfers between devices having local memories

Method of and apparatus for store-in second level cache flush

Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks

System and method for performing conflict resolution and flow control in a multiprocessor system

Message flow protocol for avoiding deadlocks

Multi-processor data processing system with multiple second level caches mapable to all of addressable memory

Memory queue with adjustable priority and conflict detection

System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions

Method and apparatus for efficiently generating test input for a logic simulator

Programmable system and method for accessing a shared memory

System and method for providing speculative ownership of cached data based on history tracking

Directory-based cache coherency system supporting multiple instruction processor and input/output caches

Directory based cache coherency system supporting multiple instruction processor and input/output caches

Selectable two-way, four-way double cache interleave scheme

Cache-level return data by-pass system for a hierarchical memory

System and method for providing the speculative return of cached data within a hierarchical memory system

System and method for providing speculative arbitration for transferring data

Second level cache having instruction cache parity error control

System and method for performing error recovery in a data processing system having multiple processing partitions

System and method for accelerating read requests within a multiprocessor system

System and method for accelerating ownership within a directory-based memory system

Method of and apparatus for serial dynamic system partitioning

Test driver for use in validating a circuit design

Method and apparatus for synchronizing independently executing test lists for design verification

Source synchronous transfer scheme for a high speed memory interface

Data acceleration mechanism for a multiprocessor shared memory system

Dayclock carry and compare tree

Leaky cache mechanism

Main memory interface for high speed data transfer

Method and apparatus for parallel store-in second level caching

System and method for testing and initializing directory store memory

Apparatus and method for analyzing performance of a data processing system

Familial correction with non-familial double bit error detection

Operand and limits optimization for binary translation system

Reduced instruction processor/storage controller interface

Interface queue with bypassing capability for main storage unit

(unassigned)

Dynamic power regulator for controlling memory power consumption

HONEYWELL INC

Dual slope analog to digital converter with out-of-range reset