Inventor

HSIEH CHING-HUA

TW220 patents

⚠️ This page may combine multiple inventors who share the name “HSIEH CHING-HUA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSIEH CHING-HUA

TAIWAN SEMICONDUCTOR MFG CO LTD

Package-on-package structure and method

Package structure and method for forming the same

Aligning bumps in fan-out packaging process

Integrated fan-out packages with embedded heat dissipation structure

Semiconductor package, manufacturing method of semiconductor device and semiconductor package

Package structure

Package and manufacturing method thereof

Electronic device and manufacturing method thereof

Semiconductor package and method of fabricating the same

Structure and formation method of chip package with fan-out structure

Integrated fan-out package and method of fabricating the same

Package structure and method for forming the same

Integrated fan-out package and method of fabricating the same

Package structure and method for forming the same

Copper contact plugs with barrier layers

Semiconductor devices and methods of forming same

Package structure and method of fabrcating the same

Method of manufacturing integrated fan-out package

Semiconductor structure and manufacturing method thereof

Semiconductor package and method of fabricating the same

Semiconductor device having antenna on chip package and manufacturing method thereof

Semiconductor packages

Package structure

Package structure

Package structure with porous conductive structure and manufacturing method thereof

TAIWAN SEMICONDUCTOR MFG

Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomic layer deposition for deep sub-micron semiconductor technology

Method of barrier-less integration with copper alloy

Barrier layer for copper interconnect

Cleaning processes in the formation of integrated circuit interconnect structures

Barrier structure for semiconductor devices

Adhesion of copper and etch stop layer for copper alloy

Bond pad for flip chip package

Methods for edge alignment mark protection during damascene electrochemical plating of copper

Structure and method for forming interconnect structure

Methods for optimizing conductor patterns for ECP and CMP in semiconductor processing

Multi-step Cu seed layer formation for improving sidewall coverage

Barrier layer and fabrication method thereof

Method for high kinetic energy plasma barrier deposition

Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers

Reducing resistivity in interconnect structures by forming an inter-layer

High performance metallization cap layer

Barrier-less integration with copper alloy

Barrier metal re-distribution process for resistivity reduction

Method for simultaneous degas and baking in copper damascene process

Photoresist scum for copper dual damascene process

Method for reducing surface defects in an electrodeposition process

SHUE SHAU-LIN

Methods for via structure with improved reliability

Via structure with improved reliability

CHANG CHUNG-LIANG

Barrier material and process for Cu interconnect

SU LI-LIN

Copper contact plugs with barrier layers