Inventor

LIU JINPING

US104 patents

⚠️ This page may combine multiple inventors who share the name “LIU JINPING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU JINPING

GLOBALFOUNDRIES INC

Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs

Method for improved fin profile

10 nm alternative N/P doped fin for SSRW scheme

Methods of forming gate structures for transistor devices for CMOS applications

Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks

Multiple-layer spacers for field-effect transistors

Advanced method for scaled SRAM with flexible active pitch

Method to form wrap-around contact for finFET

Sub-fin doping method

Devices and methods of forming SADP on SRAM and SAQP on logic

Semiconductor device with diffusion barrier film and method of manufacturing the same

Silicon liner for STI CMP stop in FinFET

Self-aligned lithographic patterning with variable spacings

Integrated circuits and methods for their fabrication

Gate structures for transistor devices for CMOS applications and products

Method for eliminating interlayer dielectric dishing and controlling gate height uniformity

Methods of forming fins with different fin heights

Field effect transistors with reduced parasitic resistances and method

Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

Method for forming single diffusion breaks between finFET devices and the resulting devices

Self-aligned multiple patterning processes with layered mandrels

Methods, apparatus, and system for a semiconductor device comprising gates with short heights

Field-effect transistors with fins formed by a damascene-like process

Active gate contacts and method of fabrication thereof

Fabrication of multi threshold-voltage devices

Contact etch stop layer with sacrificial polysilicon layer

Method of adjusting spacer thickness to provide variable threshold voltages in FinFETs

Wrap-around contact for finFET

Multi-step insulator formation in trenches to avoid seams in insulators

Methods, apparatus and system for self-aligned metal hard masks

Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors

Methods of forming replacement gate structures on transistor devices

Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same

Methods of forming spacers on FinFET devices

Integrated circuits having finFETs with improved doped channel regions and methods for fabricating same

Forming defect-free relaxed SiGe fins

Protected trench isolation for fin-type field-effect transistors

Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask

CHARTERED SEMICONDUCTOR MFG

Material architecture for the fabrication of low temperature transistor

End of range (EOR) secondary defect engineering using substitutional carbon doping

Implantation-less approach to fabricating strained semiconductor on isolation wafers

GLOBALFOUNDRIES US INC

IC product comprising an insulating gate separation structure positioned between end surfaces of adjacent gate structures

Transistor comprising an air gap positioned adjacent a gate electrode

FinFET device comprising a single diffusion break with an upper surface that is substantially coplanar with an upper surface of a fin

LIU YANXIANG

Transistor with reduced parasitic capacitance

Methods for fabricating a FINFET integrated circuit on a bulk silicon substrate

RES CORP TECHNOLOGIES INC

Reagents for detection of primary amines

Quinoline-2-(carboxaldehyde) reagents for detection of primary amines

GLOBALFOUNDRIES SG PTE LTD

Method for fabricating a semiconductor device having an epitaxial channel and transistor having same

LIU JINPING

Integrated circuit and method of fabrication thereof