Inventor

LEE JAE-GON

KR114 patents

⚠️ This page may combine multiple inventors who share the name “LEE JAE-GON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE JAE-GON

SAMSUNG ELECTRONICS CO LTD

Clock management using full handshaking

Memory module, operation method therof, and operation method of host

Semiconductor device including clock management unit for outputing clock and acknowledgement signals to an intellectual property block

Semiconductor device, semiconductor system and method for operating semiconductor device

Semiconductor device including clock generating circuit and channel management circuit

Memory expander, heterogeneous computing device using memory expander, and operation method of heterogenous computing

Metamaterial structure antenna and metamaterial structure array

Magnetic recording/reproducing apparatus

Semiconductor device, semiconductor system, and method of operating the semiconductor device

Semiconductor device

Semiconductor device

Semiconductor device

Semiconductor device

GLOBALFOUNDRIES INC

Stacked nanosheet field-effect transistor with diode isolation

Scaled gate contact and source/drain cap

Scaled memory structures or other logic devices with middle of the line cuts

Vertical FINFET structure and methods of forming same

Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method

FinFETs having gates parallel to fins

Scaled gate contact and source/drain cap

TOH ENG HUAT

FinFET with stressors

LDMOS with two gate stacks having different work functions for improved breakdown voltage

Finfet

LDMOS with improved breakdown voltage

Non-volatile memory utilizing impact ionization and tunnelling and method of manufacturing thereof

Methods to reduce gate contact resistance for AC reff reduction

CHARTERED SEMICONDUCTOR MFG

Integrated circuit system for suppressing short channel effects

Method for integrating a SONOS gate oxide transistor into a logic/analog integrated circuit having several gate oxide thicknesses

Selective STI stress relaxation through ion implantation

Enhanced stress for transistors

Avoiding plasma charging in integrated circuits

GLOBALFOUNDRIES SG PTE LTD

LDMOS with improved breakdown voltage

Semiconductor device with reduced contact resistance and method of manufacturing thereof

Channel surface technique for fabrication of FinFET devices

FinFET

LEE JAE GON

System on chip, devices having the same, and method for power control of the SOC

Integrated circuit system employing stress-engineered spacers

KIM DONG KEUN

Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same

Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same

LEE JAE-GON

Method of performing dynamic voltage and frequency scaling operation, application processor performing method, and mobile device comprising application processor

Methods of spreading plurality of interrupts, interrupt request signal spreader circuits, and systems-on-chips having the same

KT & G CORP

Method and apparatus for manufacturing flavor capsule of tobacco

Method and apparatus for manufacturing flavor capsule of tobacco

TAN CHUNG FOONG

Channel surface technique for fabrication of FinFET devices

UTOMO HENRY K

Method of forming source and drain of field-effect-transistor and structure thereof

YIN CHUNSHAN

FinFET with novel body contact for multiple Vt applications

JEONG BUB-CHUL

Asynchronous bridge

HONGIK UNIV INDUSTRY ACADEMIA COOPERATION FOUNDATION

Apparatus for transmitting simultaneous multiple beams to multiple targets at near field and far field

CHOI YOUN-SIK

System-on-chip to support full handshake and mobile device having the same

TAN SHYUE SENG

Integrated circuit system employing resistance altering techniques