Inventor
FETTERMAN MICHAEL
US18 patents
⚠️ This page may combine multiple inventors who share the name “FETTERMAN MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FETTERMAN MICHAEL
7 patentsUS9262174B2Feb 16, 2016
Dynamic bank mode addressing for memory access
FETTERMAN MICHAEL8 citations82
US10095548B2Oct 9, 2018
Mechanism for waking common resource requests within a resource management subsystem
FETTERMAN MICHAEL5 citations71
US10007527B2Jun 26, 2018
Uniform load processing for parallel thread sub-sets
FETTERMAN MICHAEL1 citations50
US9755994B2Sep 5, 2017
Mechanism for tracking age of common resource requests within a resource management subsystem
FETTERMAN MICHAEL1 citations50
US9836325B2Dec 5, 2017
Resource management subsystem that maintains fairness and order
FETTERMAN MICHAEL0 citations40
US10152329B2Dec 11, 2018
Pre-scheduled replays of divergent operations
FETTERMAN MICHAEL0 citations39
US9817668B2Nov 14, 2017
Batched replays of divergent operations
FETTERMAN MICHAEL0 citations39
INTEL CORP
4 patentsUS7500049B2Mar 3, 2009
Providing a backing store in user-level memory
INTEL CORP8 citations83
US7404065B2Jul 22, 2008
Flow optimization and prediction for VSSE memory operations
INTEL CORP7 citations73
US7457932B2Nov 25, 2008
Load mechanism
INTEL CORP0 citations52
US7457938B2Nov 25, 2008
Staggered execution stack for vector processing
INTEL CORP1 citations52
NVIDIA CORP
4 patentsUS11934311B2Mar 19, 2024
Hybrid allocation of data lines in a streaming cache memory
NVIDIA CORP0 citations62
US11823318B2Nov 21, 2023
Techniques for interleaving textures
NVIDIA CORP0 citations61
US11379944B2Jul 5, 2022
Techniques for performing accelerated point sampling in a texture processing pipeline
NVIDIA CORP1 citations56
US12314175B2May 27, 2025
Cache memory with per-sector cache residency controls
NVIDIA CORP0 citations51