Inventor

EDMONDSON JOHN H

US47 patents

⚠️ This page may combine multiple inventors who share the name “EDMONDSON JOHN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EDMONDSON JOHN H

NVIDIA CORP

Memory addressing controlled by PTE fields

Mapping memory partitions to virtual memory pages

Memory addressing scheme using partition strides

Connecting multiple pixel shaders to a frame buffer without a crossbar

Method and system for reducing memory bandwidth requirements in an anti-aliasing operation

Method and apparatus for providing peer-to-peer data transfer within a computing environment

Compression tag state interlock

Hierarchical flush barrier mechanism with deadlock avoidance

Page stream sorter for poor locality access patterns

Method and apparatus for providing peer-to-peer data transfer within a computing environment

Supporting late DRAM bank hits

Technique for reducing voltage droop by throttling instruction issue rate

Dynamically detecting uniformity and eliminating redundant computations to reduce power consumption

High-density latch arrays

Systems for efficient retrieval from tiled memory surface to linear memory display

DIGITAL EQUIPMENT CORP

Method and apparatus for predicting memory dependence using store sets

Ensuring write ordering under writeback cache error conditions

Combined write-operand queue and read-after-write dependency scoreboard

Pipelined computer with operand context queue to simplify context-dependent execution flow

Fast area-efficient multi-bit binary adder with low fan-out signals

Method for increasing system bandwidth through an on-chip address lock register

System interface protocol with optional module cache

EDMONDSON JOHN H

Cache and associated method with frame buffer managed dirty data pull and high-priority clean mechanism

System and method for cleaning dirty data in a cache via frame buffer logic

Coalescing to avoid read-modify-write during compressed data operations

Coalescing to avoid read-modify-write during compressed data operations

Supporting late DRAM bank hits

Coalescing to avoid read-modify-write during compressed data operations

VAN DYKE JAMES M

Graphics system with virtual memory pages and non-power of two number of memory elements

Compressed data access system and method

Compression tag state interlock

Early compression tag lookup for memory accesses

KEIL SHANE

Managing conflicts on shared L2 bus

Managing conflicts on shared L2 bus

Sorting requests to the DRAM for high page locality

GLASCO DAVID B

System, method and frame buffer logic for evicting dirty data from a cache using counters and data types

Techniques for evicting dirty data from a cache using a notification sorter and count thresholds

Virtual channels for effective packet transfer

FETTERMAN MICHAEL

Mechanism for waking common resource requests within a resource management subsystem

Mechanism for tracking age of common resource requests within a resource management subsystem

Resource management subsystem that maintains fairness and order

ROBERTS JAMES

Using a data cache array as a DRAM load/store buffer

Configurable cache occupancy policy

COMPAQ COMPUTER CORP

Method and apparatus for predicting multiple conditional branches

RAMBUS INC

Digital clock recovery circuit

DUNCAN SAMUEL HAMMOND

Bandwidth impedance matching and starvation avoidance by read completion buffer allocation

YU SHU-YI

Approach for allocating virtual bank managers within a dynamic random access memory (DRAM) controller to physical banks within a DRAM