Inventor

SELVANESAN RAJESHWARAN

US20 patents

⚠️ This page may combine multiple inventors who share the name “SELVANESAN RAJESHWARAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SELVANESAN RAJESHWARAN

FETTERMAN MICHAEL

Dynamic bank mode addressing for memory access

Mechanism for waking common resource requests within a resource management subsystem

Uniform load processing for parallel thread sub-sets

Mechanism for tracking age of common resource requests within a resource management subsystem

Resource management subsystem that maintains fairness and order

Pre-scheduled replays of divergent operations

Batched replays of divergent operations

MINKIN ALEXANDER L

Cache arbitration between multiple clients

Cache miss processing using a defer/replay mechanism

Cache interface protocol including arbitration and hints

Configurable cache for multiple clients

Sharing data crossbar for reads and writes in a data cache

NVIDIA CORP

Techniques for configuring a processor to execute instructions efficiently

Techniques for efficiently operating a processing system based on energy characteristics of instructions and machine learning

Method and system for automating unit performance testing in integrated circuit design

PURCELL STEPHEN CLARK

Method and apparatus for generating random numbers for use in a field programmable gate array

Method and apparatus for generating random numbers for use in a field programmable gate array

HEINRICH STEVEN JAMES

Cache operations and policies for a multi-threaded client

CHOQUETTE JACK HILAIRE

Shaped register file reads

PASTEMAK SOLUTIONS LLC

Method and apparatus for generating random numbers for use in a field programmable gate array