Inventor
MATHENY ADAM P
US20 patents
⚠️ This page may combine multiple inventors who share the name “MATHENY ADAM P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
19 patentsUS7581201B2Aug 25, 2009
System and method for sign-off timing closure of a VLSI chip
IBM35 citations90
US6958545B2Oct 25, 2005
Method for reducing wiring congestion in a VLSI chip design
IBM8 citations72
US9886541B2Feb 6, 2018
Process for improving capacitance extraction performance
IBM4 citations70
US9934341B2Apr 3, 2018
Simulation of modifications to microprocessor design
IBM2 citations69
US10360338B2Jul 23, 2019
Method for improving capacitance extraction performance by approximating the effect of distant shapes
IBM5 citations68
US7904861B2Mar 8, 2011
Method, system, and computer program product for coupled noise timing violation avoidance in detailed routing
IBM2 citations58
US11341311B1May 24, 2022
Generation and selection of universally routable via mesh specifications in an integrated circuit
IBM1 citations54
US9256705B2Feb 9, 2016
Reducing repeater power
IBM0 citations51
US11875099B2Jan 16, 2024
Noise impact on function (NIOF) reduction for integrated circuit design
IBM0 citations50
US9785735B1Oct 10, 2017
Parallel incremental global routing
IBM1 citations50
US10354041B2Jul 16, 2019
Process for improving capacitance extraction performance
IBM0 citations49
US10169526B2Jan 1, 2019
Incremental parasitic extraction for coupled timing and power optimization
IBM0 citations49
US10169516B2Jan 1, 2019
Methods and computer program products for via capacitance extraction
IBM0 citations49
US9858383B2Jan 2, 2018
Incremental parasitic extraction for coupled timing and power optimization
IBM1 citations49
US9928322B2Mar 27, 2018
Simulation of modifications to microprocessor design
IBM0 citations48
US8032851B2Oct 4, 2011
Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit
IBM0 citations48
US8006208B2Aug 23, 2011
Reducing coupling between wires of an electronic circuit
IBM0 citations48
US11941340B2Mar 26, 2024
Cross-hierarchy antenna condition verification
IBM0 citations46
US10331840B2Jun 25, 2019
Resource aware method for optimizing wires for slew, slack, or noise
IBM0 citations30