Inventor
TKACHEV YURI
US13 patents
⚠️ This page may combine multiple inventors who share the name “TKACHEV YURI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SILICON STORAGE TECH INC
11 patentsUS7868375B2Jan 11, 2011
Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
SILICON STORAGE TECH INC230 citations98
US7927994B1Apr 19, 2011
Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing
SILICON STORAGE TECH INC73 citations97
US9123822B2Sep 1, 2015
Split gate non-volatile flash memory cell having a silicon-metal floating gate and method of making same
SILICON STORAGE TECH INC10 citations83
US9245638B2Jan 26, 2016
Method of operating a split gate flash memory cell with coupling gate
SILICON STORAGE TECH INC11 citations82
US10714489B2Jul 14, 2020
Method of programming a split-gate flash memory cell with erase gate
SILICON STORAGE TECH INC2 citations73
US9633735B2Apr 25, 2017
System and method to inhibit erasing of portion of sector of split gate flash memory cells
SILICON STORAGE TECH INC2 citations71
US11018147B1May 25, 2021
Method of forming split gate memory cells with thinned tunnel oxide
SILICON STORAGE TECH INC3 citations68
US11393535B2Jul 19, 2022
Ultra-precise tuning of analog neural memory cells in a deep learning artificial neural network
SILICON STORAGE TECH INC0 citations61
US9275748B2Mar 1, 2016
Low leakage, low threshold voltage, split-gate flash cell operation
SILICON STORAGE TECH INC2 citations59
US12020762B2Jun 25, 2024
Method of determining defective die containing non-volatile memory cells
SILICON STORAGE TECH INC0 citations46
US11362218B2Jun 14, 2022
Method of forming split gate memory cells with thinned side edge tunnel oxide
SILICON STORAGE TECH INC0 citations46