P

Inventor

HOW DANA

US40 patents
⚠️ This page may combine multiple inventors who share the name “HOW DANA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALTERA CORP

28 patents
US10333535B1Jun 25, 2019

Techniques for signal skew compensation

ALTERA CORP11 citations84
US9685957B2Jun 20, 2017

System reset controller replacing individual asynchronous resets

ALTERA CORP8 citations84
US9553762B1Jan 24, 2017

Network-on-chip with fixed and configurable functions

ALTERA CORP11 citations84
US9503057B1Nov 22, 2016

Clock grid for integrated circuit

ALTERA CORP9 citations84
US9479456B2Oct 25, 2016

Programmable logic device with integrated network-on-chip

ALTERA CORP15 citations84
US9922157B1Mar 20, 2018

Sector-based clock routing methods and apparatus

ALTERA CORP14 citations83
US9588176B1Mar 7, 2017

Techniques for using scan storage circuits

ALTERA CORP9 citations82
US9501092B1Nov 22, 2016

Systems and methods for clock alignment using pipeline stages

ALTERA CORP5 citations80
US10523207B2Dec 31, 2019

Programmable circuit having multiple sectors

ALTERA CORP6 citations73
US9946826B1Apr 17, 2018

Circuit design implementations in secure partitions of an integrated circuit

ALTERA CORP6 citations73
US9606573B1Mar 28, 2017

Configurable clock grid structures

ALTERA CORP6 citations73
US9250859B2Feb 2, 2016

Deterministic FIFO buffer

ALTERA CORP3 citations73
US9843332B1Dec 12, 2017

Clock grid for integrated circuit

ALTERA CORP1 citations63
US9385717B1Jul 5, 2016

Level-sensitive two-phase single-wire latch controllers without contention

ALTERA CORP2 citations63
US9172379B1Oct 27, 2015

Efficient controllers and implementations for elastic buffers

ALTERA CORP3 citations63
US10367745B1Jul 30, 2019

Network-on-chip with fixed and configurable functions

ALTERA CORP1 citations62
US10523224B2Dec 31, 2019

Techniques for signal skew compensation

ALTERA CORP0 citations52
US10367756B2Jul 30, 2019

Programmable logic device with integrated network-on-chip

ALTERA CORP0 citations52
US10044344B2Aug 7, 2018

Systems and methods for a low hold-time sequential input stage

ALTERA CORP0 citations52
US9806696B1Oct 31, 2017

Systems and methods for a low hold-time sequential input stage

ALTERA CORP0 citations52
US9698784B1Jul 4, 2017

Level-sensitive two-phase single-wire latch controllers without contention

ALTERA CORP0 citations52
US9660630B1May 23, 2017

Clock grid for integrated circuit

ALTERA CORP0 citations52
US10591544B2Mar 17, 2020

Programmable integrated circuits with in-operation reconfiguration capability

ALTERA CORP0 citations51
US10082541B2Sep 25, 2018

Mixed redundancy scheme for inter-die interconnects in a multichip package

ALTERA CORP0 citations51
US9960903B1May 1, 2018

Systems and methods for clock alignment using pipeline stages

ALTERA CORP0 citations48
US10210919B2Feb 19, 2019

Integrated circuits with embedded double-clocked components

ALTERA CORP0 citations42
US9703526B2Jul 11, 2017

Self-stuffing multi-clock FIFO requiring no synchronizers

ALTERA CORP0 citations42
US9602587B2Mar 21, 2017

Multiple plane network-on-chip with master/slave inter-relationships

ALTERA CORP0 citations42

LIGHTSPEED SEMICONDUCTOR CORP

7 patents

AGATE LOGIC INC

2 patents

SCHMIT HERMAN

1 patent

INTEL CORP

1 patent

HOW DANA

1 patent