Inventor

MUKHERJEE NILOY

US246 patents

⚠️ This page may combine multiple inventors who share the name “MUKHERJEE NILOY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUKHERJEE NILOY

INTEL CORP

Transistors with high concentration of boron doped germanium

Methods of forming nickel sulfide film on a semiconductor device

Transistors with high concentration of germanium

Transition metal dichalcogenides (TMDCS) over III-nitride heteroepitaxial layers

Group III-N nanowire transistors

Techniques for forming non-planar resistive memory cells

Group III-N nanowire transistors

Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

Deep gate-all-around semiconductor device having germanium or group III-V active layer

III-N material structure for gate-recessed transistors

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Techniques for filament localization, edge effect reduction, and forming/switching voltage reduction in RRAM devices

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

III-N material structure for gate-recessed transistors

Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes

Group III-N nanowire transistors

Lattice mismatched hetero-epitaxial film

ORACLE INT CORP

Mirroring, in memory, data from disk to improve query performance

Core in-memory space and object management architecture in a traditional RDBMS supporting DW and OLTP applications

Method and system for log structured relational database objects

Readable physical storage replica and standby database system

Optimizing execution plans for in-memory-aware joins

Prioritizing repopulation of in-memory compression units

Sharding of in-memory objects across NUMA nodes

Framework for numa affinitized parallel query on in-memory objects within the RDBMS

CONFLUERA INC

Detecting and trail-continuation for attacks through remote desktop protocol lateral movement

Methods and systems for identifying infrastructure attack progressions

Methods and system for identifying relationships among infrastructure security-related events

Methods and system for tracking security risks over infrastructure

Methods and system for detecting behavioral indicators of compromise in infrastructure

Attack detection based on graph edge context

Methods and system for characterizing infrastructure security-related events

PILLARISETTY RAVI

Trench confined epitaxially grown device layer(s)

Non-planar germanium quantum well devices

Trench confined epitaxially grown device layer(s)

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

Non-planar germanium quantum well devices

RADOSAVLJEVIC MARKO

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Conductivity improvements for III-V semiconductor devices

Non-planar semiconductor device having channel region with low band-gap cladding layer

THEN HAN WUI

Group III-N nanowire transistors

High voltage field effect transistors

Non-planar III-N transistor

KEPLER COMPUTING INC

Ferroelectric device film stacks with texturing layer, and method of forming such

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication

Memory devices with dual encapsulation layers and methods of fabrication

MUKHERJEE NILOY

Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions

Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes

MURTHY ANAND S

Transistors with high concentration of boron doped germanium

DEWEY GILBERT

Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack