Inventor

METZ MATTHEW V

US244 patents

⚠️ This page may combine multiple inventors who share the name “METZ MATTHEW V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

METZ MATTHEW V

INTEL CORP

Multilayer metal gate electrode

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Dielectric interface for group III-V semiconductor device

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

Device with scavenging spacer layer

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Methods for integrating replacement metal gate structures

Replacement gate process for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

CMOS device with metal and silicide gate electrodes and a method for making it

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Semiconductor device with a high-k gate dielectric and a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode

Fabrication of germanium nanowire transistors

Method for making a semiconductor device having a high-k gate dielectric

Method for fabricating transistor with thinned channel

Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Forming high-k dielectric layers on smooth substrates

Method for making a semiconductor device that includes a metal gate electrode

Planarizing a semiconductor structure to form replacement metal gates

Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit

Method for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device having a high-k gate dielectric

Dielectric interface for group III-V semiconductor device

Inducing strain in the channels of metal gate transistors

Forming integrated circuits with replacement metal gate electrodes

Method of forming abrupt source drain metal gate transistors

Selective high-k dielectric film deposition for semiconductor device

Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors

Method for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device having a high-K gate dielectric and a titanium carbide gate electrode

Method for making a semiconductor device that includes a metal gate electrode

Reducing the dielectric constant of a portion of a gate dielectric

Method for making a semiconductor device having a high-k gate dielectric

Method for making a semiconductor device with a metal gate electrode

Method for making a semiconductor device with a high-k gate dielectric and metal layers that meet at a P/N junction

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Angled implantation for removal of thin film layers

Forming dual metal complementary metal oxide semiconductor integrated circuits

Method for etching a thin metal layer

PILLARISETTY RAVI

Trench confined epitaxially grown device layer(s)

Trench confined epitaxially grown device layer(s)

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

MUKHERJEE NILOY

Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions

Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes

JIN BEEN-YIH

Fabrication of germanium nanowire transistors

KAVALIEROS JACK T

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

DATTA SUMAN

Inducing strain in the channels of metal gate transistors