Inventor

LE VAN H

US234 patents

⚠️ This page may combine multiple inventors who share the name “LE VAN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LE VAN H

INTEL CORP

Conversion of strain-inducing buffer to electrical insulator

Top-gate doped thin film transistor

Thin film transistors having U-shaped features

Quantum dot devices with modulation doped stacks

Vertical 1T-1C DRAM array

Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits

Non-planar gate all-around device and method of fabrication thereof

Ge nano wire transistor with GaAs as the sacrificial layer

Semiconductor device having germanium active layer with underlying diffusion barrier layer

Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

Variable gate width for gate all-around transistors

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

Lattice mismatched hetero-epitaxial film

Stain compensation in transistors

Fabrication of non-planar IGZO devices for improved electrostatics

Quantum dot devices with fins

Direct bonding in microelectronic assemblies

Thin film transistors for high voltage applications

Integrated circuit assemblies

Transistors, memory cells, and arrangements thereof

Top-gate doped thin film transistor

Multi-chip module having a stacked logic chip and memory stack

Structures and methods for memory cells

Metallic sealants in transistor arrangements

Memory cells based on vertical thin-film transistors

Nanowire thin film transistors with textured semiconductors

Vertical thin-film transistors between metal layers

Double gated thin film transistors

Contact electrodes and dielectric structures for thin film transistors

Quantum dot devices with back gates

Threshold switching selector based memory

Stacked thin film transistors with nanowires

Fully self-aligned cross grid vertical memory array

PILLARISETTY RAVI

Trench confined epitaxially grown device layer(s)

Trench confined epitaxially grown device layer(s)

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Techniques and configuration for stacking transistors of an integrated circuit device

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer

RACHMADY WILLY

Non-planar gate all-around device and method of fabrication thereof

Semiconductor devices with germanium-rich active layers and doped transition layers

Variable gate width for gate all-around transistors

Non-planar quantum well device having interfacial layer and method of forming same

MARK IV IND LTD

Board for mounting display element

Board for mounting display element

CAPPELLANI ANNALISA

Conversion of strain-inducing buffer to electrical insulator

GOEL NITI

Epitaxial film growth on patterned substrate