Inventor

CHU-KUNG BENJAMIN

US198 patents

⚠️ This page may combine multiple inventors who share the name “CHU-KUNG BENJAMIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHU-KUNG BENJAMIN

INTEL CORP

Thin film transistors having U-shaped features

Source/drain diffusion barrier for germanium NMOS transistors

Group III-N nanowire transistors

Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices

III-N epitaxial device structures on free standing silicon mesas

Group III-N nanowire transistors

Group III-N transistor on nanoscale template structures

Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Forming LED structures on silicon fins

Nonplanar III-N transistors with compositionally graded semiconductor channels

III-N material structure for gate-recessed transistors

Group III-N transistors on nanoscale template structures

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

III-N material structure for gate-recessed transistors

Group III-N nanowire transistors

Lattice mismatched hetero-epitaxial film

Nonplanar III-N transistors with compositionally graded semiconductor channels

Group III-N transistors on nanoscale template structures

Stain compensation in transistors

Techniques for forming non-planar germanium quantum well devices

III-N material structure for gate-recessed transistors

Techniques for forming non-planar germanium quantum well devices

Defect transferred and lattice mismatched epitaxial film

Techniques for forming contacts to quantum well transistors

Self-aligned tunneling pocket in field-effect transistors and processes to form same

PILLARISETTY RAVI

Non-planar germanium quantum well devices

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors

Non-planar germanium quantum well devices

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Techniques for forming contacts to quantum well transistors

Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer

Germanium-based quantum well devices

Germanium-based quantum well devices

Modulation-doped halo in quantum well field-effect transistors, apparatus made therewith, and methods of using same

THEN HAN WUI

Group III-N nanowire transistors

High voltage field effect transistors

Nonplanar III-N transistors with compositionally graded semiconductor channels

Group III-N transistors on nanoscale template structures

Non-planar III-N transistor

III-N material structure for gate-recessed transistors

Group III-N transistors on nanoscale template structures

RADOSAVLJEVIC MARKO

CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture

Non-planar semiconductor device having channel region with low band-gap cladding layer

DEWEY GILBERT

Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack

Non-planar semiconductor device having active region with multi-dielectric gate stack

KOTLYAR ROZA

Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs