Inventor

GOEL NITI

US35 patents

⚠️ This page may combine multiple inventors who share the name “GOEL NITI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOEL NITI

INTEL CORP

Tunnel field effect transistor and method of manufacturing same

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

Lattice mismatched hetero-epitaxial film

Defect transferred and lattice mismatched epitaxial film

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

Cladding layer epitaxy via template engineering for heterogeneous integration on silicon

Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy

Selective epitaxially grown III-V materials based devices

Conductivity improvements for III-V semiconductor devices

Methods and structures to prevent sidewall defects during selective epitaxy

Selective epitaxially grown III-V materials based devices

Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation

Decoupling capacitors and arrangements

Methods of containing defects for non-silicon device engineering

Techniques to achieve area reduction through co-optimizing logic core blocks and memory redundancies

Selective epitaxially grown III-V materials based devices

Making a defect free fin based device in lateral epitaxy overgrowth region

Methods and structures to prevent sidewall defects during selective epitaxy

GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation

Nanoscale structure with epitaxial film having a recessed bottom portion

Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon

Methods of containing defects for non-silicon device engineering

Making a defect free fin based device in lateral epitaxy overgrowth region

Techniques for forming a compacted array of functional cells

PILLARISETTY RAVI

Trench confined epitaxially grown device layer(s)

Trench confined epitaxially grown device layer(s)

Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer

GOEL NITI

Epitaxial film growth on patterned substrate

Tunnel field effect transistor and method of manufacturing same

Methods of containing defects for non-silicon device engineering

MUKHERJEE NILOY

Methods to enhance doping concentration in near-surface layers of semiconductors and methods of making same

Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby

RADOSAVLJEVIC MARKO

Conductivity improvements for III-V semiconductor devices

DASGUPTA SANSAPTAK

Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation