Inventor

TOLCHINSKY PETER G

US20 patents

⚠️ This page may combine multiple inventors who share the name “TOLCHINSKY PETER G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TOLCHINSKY PETER G

INTEL CORP

Transistors with increased mobility in the channel zone and method of fabrication

Dislocation-free InSb quantum well structure on Si using novel buffer architecture

Buffer layers for device isolation of devices grown on silicon

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition

Methods of forming buffer layer architecture on silicon and structures formed thereby

GaN devices on engineered silicon substrates

Dislocation removal from a group III-V film grown on a semiconductor substrate

High hole mobility p-channel Ge transistor structure on Si substrate

Silicon PMOS with gallium nitride NMOS for voltage regulation

Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer

Method for making a semiconductor device having increased carrier mobility

Method of forming silicon on insulator wafers

Methods of vertically stacking wafers using porous silicon

Techniques for monolithic co-integration of silicon and III-N semiconductor transistors

Buffer layers for device isolation of devices grown on silicon

HUDAIT MANTU K

Stacking fault and twin blocking barrier for integrating III-V on Si

Stacking fault and twin blocking barrier for integrating III-V on Si

High hole mobility p-channel Ge transistor structure on Si substrate

CAPPELLANI ANNALISA

Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition

MUKHERJEE NILOY

Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby