Inventor

CHAU ROBERT S

US419 patents

⚠️ This page may combine multiple inventors who share the name “CHAU ROBERT S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAU ROBERT S

INTEL CORP

Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material

Field effect transistor with narrow bandgap source and drain regions and method of fabrication

Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers

Tri-gate devices and methods of fabrication

Nonplanar device with stress incorporation layer and method of fabrication

Carbon nanotube energy well (CNEW) field effect transistor

Multilayer metal gate electrode

Nonplanar transistors with metal gate electrodes

MOSFET gate electrodes having performance tuned work functions and methods of making same

Tri-gate devices and methods of fabrication

Nonplanar device with stress incorporation layer and method of fabrication

Tri-gate devices and methods of fabrication

Nonplanar device with stress incorporation layer and method of fabrication

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Semiconductor transistor having a stressed channel

Semiconductor transistor having a stressed channel

Tri-gate devices and methods of fabrication

MOS transistor structure and method of fabrication

Transistor structure and method of fabrication

Semiconductor transistor having a stressed channel

Cobalt salicidation method on a silicon germanium film

Transistor with low resistance tip and method of fabrication in a CMOS process

Method of frabricating a MOS transistor having a composite gate electrode

N2 O nitrided-oxide trench sidewalls and method of making isolation structure

CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers

MOS transistor having a composite gate electrode and method of fabrication

Block contact architectures for nanoscale channel transistors

Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate

Methods for patterning a semiconductor film

Multigate device with recessed strain regions

Dielectric interface for group III-V semiconductor device

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

Stacked multi-gate transistor design and method of fabrication

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode

Nonplanar transistors with metal gate electrodes

Nonplanar transistors with metal gate electrodes

Method of forming a metal oxide dielectric

Block contact architectures for nanoscale channel transistors

Device with scavenging spacer layer

Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer

Methods for integrating replacement metal gate structures

Replacement gate process for making a semiconductor device that includes a metal gate electrode

Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode

PILLARISETTY RAVI

Trench confined epitaxially grown device layer(s)

Non-planar germanium quantum well devices

MUKHERJEE NILOY

Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions

RACHMADY WILLY

Non-planar gate all-around device and method of fabrication thereof

DEWEY GILBERT

Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface