Inventor

HAFEZ WALID M

US144 patents

⚠️ This page may combine multiple inventors who share the name “HAFEZ WALID M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAFEZ WALID M

INTEL CORP

Penetrating implant for forming a semiconductor device

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process

High voltage three-dimensional devices having dielectric liners

Antifuse element using spacer breakdown

Dielectric and isolation lower fin material for fin-based electronics

Transistor architecture having extended recessed spacer and source/drain regions and method of making same

Programmable/re-programmable device in high-k metal gate MOS

Gate-all-around integrated circuit structures having depopulated channel structures

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Planar device on fin-based transistor architecture

Planar device on fin-based transistor architecture

Transistor with airgap spacer

Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection

III-N tunnel device architectures and high frequency mixers employing a III-N tunnel device

Co-integrated high performance nanoribbon transistors with high voltage thick gate finFET devices

Planar transistors with wrap-around gates and wrap-around source and drain contacts

Stacked integration of III-N transistors and thin-film transistors

Self-aligned gate endcap (SAGE) architecture having gate or contact plugs

Self-aligned gate endcap (SAGE) architecture having gate contacts

Dual fin endcap for self-aligned gate edge (SAGE) architectures

High-voltage transistor with self-aligned isolation

Antifuse with backfilled terminals

CMOS-compatible polycide fuse structure and method of fabricating same

Non-planar semiconductor device having self-aligned fin with top blocking layer

Antifuse element utilizing non-planar topology

Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

Gate-all-around integrated circuit structures having dual nanoribbon channel structures

Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls

Depletion mode gate in ultrathin FINFET based architecture

On-chip through-body-via capacitors and techniques for forming same

Multi-gate transistor with variably sized fin

Metal fuse and self-aligned gate edge (SAGE) architecture having a metal fuse

High-voltage transistor with self-aligned isolation

Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications

Logic circuit with indium nitride quantum well

Dielectric and isolation lower fin material for fin-based electronics

HAFEZ WALID M

Memory cell using BTI effects in high-k metal gate MOS

Antifuse element utilizing non-planar topology

High voltage three-dimensional devices having dielectric liners

High voltage three-dimensional devices having dielectric liners

Method of forming programmable anti-fuse element

YEH JENG-YA D

Precision resistor for non-planar semiconductor device architecture

Precision resistor for non-planar semiconductor device architecture

AHSAN AKM

Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection

TSAI CURTIS

Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process

TAHOE RES LTD

Dielectric and isolation lower fin material for fin-based electronics