P

Inventor

KILCOYNE SEAN P

US25 patents
⚠️ This page may combine multiple inventors who share the name “KILCOYNE SEAN P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAYTHEON CO

21 patents
US10515837B2Dec 24, 2019

Method of wafer bonding of dissimilar thickness die

RAYTHEON CO2 citations73
US10847569B2Nov 24, 2020

Wafer level shim processing

RAYTHEON CO3 citations68
US10847419B2Nov 24, 2020

Stress compensation and relief in bonded wafers

RAYTHEON CO4 citations66
US11222813B2Jan 11, 2022

Method of manufacturing wafer level low melting temperature interconnections

RAYTHEON CO0 citations62
US11710756B2Jul 25, 2023

Integrating optical elements with electro-optical sensors via direct-bond hybridization

RAYTHEON CO0 citations61
US12051712B2Jul 30, 2024

Close butted collocated variable technology imaging arrays on a single ROIC

RAYTHEON CO0 citations60
US11705471B2Jul 18, 2023

Close butted collocated variable technology imaging arrays on a single ROIC

RAYTHEON CO0 citations60
US12349475B2Jul 1, 2025

Integrated circuit having vertical routing to bond pads

RAYTHEON CO0 citations59
US12148721B2Nov 19, 2024

Iterative formation of damascene interconnects

RAYTHEON CO0 citations59
US11837623B2Dec 5, 2023

Integrated circuit having vertical routing to bond pads

RAYTHEON CO0 citations59
US11430753B2Aug 30, 2022

Iterative formation of damascene interconnects

RAYTHEON CO0 citations59
US11393869B2Jul 19, 2022

Wafer level shim processing

RAYTHEON CO0 citations58
US12278255B2Apr 15, 2025

Thin film obscurant for microelectronics

RAYTHEON CO0 citations55
US11886095B2Jan 30, 2024

Scalable unit cell device for large two-dimensional arrays with integrated phase control

RAYTHEON CO0 citations53
US10504777B2Dec 10, 2019

Method of manufacturing wafer level low melting temperature interconnections

RAYTHEON CO0 citations51
US11750945B2Sep 5, 2023

Imager with integrated asynchronous laser pulse detection having a signal component along a second electrical pathway passes through an ALPD readout integrated circuit to an imaging readout integrated circuit

RAYTHEON CO0 citations49
US10672826B2Jun 2, 2020

Segmented channel stop grid for crosstalk mitigation in visible imaging arrays

RAYTHEON CO0 citations49
US12261186B2Mar 25, 2025

Mosaic focal plane array

RAYTHEON CO0 citations48
US10879291B2Dec 29, 2020

Stacked sensor with integrated capacitors

RAYTHEON CO0 citations46
US10418406B2Sep 17, 2019

Hybrid sensor chip assembly and method for reducing radiative transfer between a detector and read-out integrated circuit

RAYTHEON CO0 citations45
US10236226B2Mar 19, 2019

In-situ calibration structures and methods of use in semiconductor processing

RAYTHEON CO0 citations36

GORE ENTERPRISE HOLDINGS INC

2 patents

VAMPOLA JOHN L

2 patents