Inventor

BHATIA AMAN

US115 patents

⚠️ This page may combine multiple inventors who share the name “BHATIA AMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BHATIA AMAN

SK HYNIX INC

Performance of a bit flipping (BF) decoder of an error correction system

Techniques for low complexity turbo product code decoding

Decoding codeword based on higher order information

Methods and memory systems for address mapping

Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes

Data storage device

Data storage device

Decoding of low-density parity-check codes with high-degree variable nodes

Memory system with decoders and method of operating such memory system and decoders

Deep learning for low-density parity-check (LDPC) decoding

Generalized product codes for flash storage

Early termination of low-density parity-check (LDPC) decoding

Systems and methods for determining change of read threshold voltage

Data storage device

Systems and methods for non-parametric PV-level modeling and read threshold voltage estimation

Compressing deep neural networks used in memory devices

Systems and methods for parametric PV-level modeling and read threshold voltage estimation

Read retry threshold optimization systems and methods conditioned on previous reads

Oscillation detection and mitigation in bit-flipping decoders

Deep learning based program-verify modeling and voltage estimation for memory devices

Memory system and method for read operation based on grouping of word lines

Efficient read-threshold calculation method for parametric PV-level modeling

Systems for adaptively determining read threshold voltage using meta information

Read threshold optimization systems and methods using model-less regression

Gaussian modeling for soft-read threshold estimation in non-volatile memory devices

Bit-flipping decoder architecture for irregular quasi-cyclic low-density parity-check codes

Dynamic control of quasi-cyclic low-density parity-check bit-flipping decoder

Data storage device

Maintaining consistent write latencies in non-volatile memory devices

Neighbor assisted correction error recovery for memory system and method thereof

Retention aware block mapping in flash-based solid state drives

Dynamic neighbor and bitline assisted correction for NAND flash storage

Read disturb detection and recovery with adaptive thresholding for 3-D NAND storage

Min-sum decoding for LDPC codes

Memory system and method for bad block management

Dynamic interleaver change for bit line failures in NAND flash storage

Soft decoder for generalized product codes

Data dependency mitigation in parallel decoders for flash storage

System and method for parallel decoding of codewords sharing common data

Memory system with on-the-fly error detection and termination and operating method thereof

Data dependency mitigation in decoder architecture for generalized product codes for flash storage

Page health prediction using product codes decoder in NAND flash storage

Low-complexity LDPC encoder

Symbol-based coding for NAND flash devices

Techniques for low-latency chase decoding of turbo product codes with soft information

Techniques for low complexity soft decoder for turbo product codes

Low latency soft decoder architecture for generalized product codes

State-based decoding of product codes

Memory system having feature boosting and operating method thereof

INTEL CORP

Techniques to use intrinsic information for a bit-flipping error correction control decoder