Inventor

BREWER TONY

US72 patents

⚠️ This page may combine multiple inventors who share the name “BREWER TONY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BREWER TONY

MICRON TECHNOLOGY INC

Method of notifying a process or programmable atomic operation traps

Detecting infinite loops in a programmable atomic transaction

Single field for encoding multiple elements

Method of notifying a process or programmable atomic operation traps

Multiple protocol header processing

Method of organizing a programmable atomic unit instruction memory

Flow control for a multiple flow control unit interface

Mapping high-speed, point-to-point interface channels to packet virtual channels

Combined write enable mask and credit return field

Initialization sequencing of chiplet I/O channels within a chiplet system

Reduced sized encoding of packet length field

Method of executing programmable atomic unit resources within a multi-process system

Detecting infinite loops in a programmable atomic transaction

Registering a custom atomic operation with the operating system

Method of completing a programmable atomic transaction by ensuring memory locks are cleared

Network credit return mechanisms

Network credit return mechanisms

Flow control for a multiple flow control unit interface

Transparent packet splitting and recombining

Reduced sized encoding of packet length field

Optional path ordering in packet-based network

Transparent packet splitting and recombining

Ordered delivery of data packets based on type of path information in each packet

Secondary device detection using a synchronous interface

Self-scheduling threads in a processor based on a threshold associated with pipeline stages

Detecting infinite loops in a programmable atomic transaction

Method of notifying a process or programmable atomic operation traps

Network credit return mechanisms

Method of organizing a programmable atomic unit instruction memory

Single field for encoding multiple elements

Programmable atomic operator resource locking

Variable pipeline length in a barrel-multithreaded processor

Self-scheduling threads in a programmable atomic unit

Programmable atomic operator resource locking

Variable pipeline length in a barrel-multithreaded processor

Managing hazards in a memory controller

Combined write enable mask and credit return field

Method for configuring multiple input-output channels

Mapping high-speed, point-to-point interface channels to packet virtual channels

Multiple protocol header processing

Deferred communications over a synchronous interface

WALLACH STEVEN J

Microprocessor architecture having alternative memory access paths

Compiler for generating an executable comprising instructions for a plurality of different instruction sets

Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set

Dispatch mechanism for dispatching instructions from a host processor to a co-processor

BREWER TONY

Systems and methods for mapping a neighborhood of data to general registers of a processing element

Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor

Multistage development workflow for generating a custom instruction set reconfigurable processor

CHIARO NETWORKS LTD

Timing and synchronization for an IP router using an optical switch

CONVEY COMPUTER

Systems and methods for selectively controlling multithreaded execution of executable code segments