Inventor

GUO TA-PEN

TW105 patents

⚠️ This page may combine multiple inventors who share the name “GUO TA-PEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUO TA-PEN

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor devices and methods of manufacture thereof

Semiconductor device including standard cells having different cell height

Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same

Self-aligned wrapped-around structure

Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

3D cross-bar nonvolatile memory

Semiconductor device including standard cell having split portions

Semiconductor device including standard cells

Integrated circuit layout method and device

Cell of transmission gate free circuit and integrated circuit layout including the same

Method of manufacturing a semiconductor device and a semiconductor device

3D cross-bar nonvolatile memory

Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

Semiconductor devices and methods of manufacture thereof

2-D material transistor with vertical structure

Enhancing integrated circuit density with active atomic reservoir

FinFET with an asymmetric source/drain structure and method of making same

Semiconductor devices and methods of manufacture thereof

Semiconductor arrangement with one or more semiconductor columns

Vertical nanowire transistor for input/output structure

Memory device and method for fabricating the same

Stacked device and associated layout structure

Gate structure and method for fabricating the same

Semiconductor device including standard cells

Method of forming semiconductor device including deep vias

Method of manufacturing a semiconductor device and a semiconductor device

Semiconductor device including deep vias, and method of generating layout diagram for same

Flip flop standard cell

Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure

2-D material transistor with vertical structure

TAIWAN SEMICONDUCTOR MFG

Self-aligned wrapped-around structure

Standard cell without OD space effect in Y-direction

Layout architecture for improving circuit performance

FinFET with an asymmetric source/drain structure and method of making same

Vertical nanowire transistor for input/output structure

Semiconductor device with reduced gate length

Integrated circuits and manufacturing methods thereof

Voltage level shifter

Structure and system of mixing poly pitch cell design under default poly pitch design rules

APTIX CORP

Structures for electrostatic discharge protection of electrical and other components

Static random access memory cell with single logic-high voltage level bit-line and address-line drivers

Programmable interconnect architecture using fewer storage cells than switches

Memory cell with user-selectable logic state on power-up

Reprogrammable interconnect architecture using fewer storage cells than switches

Memory cell with known state on power-up

High voltage random-access memory cell incorporating level shifter

Ma wei yu

Semiconductor integrated circuit having a resistor and method of forming the same

APEX SEMICONDUCTOR INC

Hidden precharge pseudo cache DRAM

DHONG SANG HOO

Planar compatible FDSOI design architecture

HOU YUNG-CHIN

Integrated circuit design using DFM-enhanced architecture