Inventor

CLIFTON PAUL A

US58 patents

⚠️ This page may combine multiple inventors who share the name “CLIFTON PAUL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CLIFTON PAUL A

ACORN TECH INC

Strained silicon with elastic edge relaxation

Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layer

MIS contact structure with metal oxide conductor

Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers

Tensile strained semiconductor photon emission and detection devices and integrated photonics system

Tensile strained semiconductor photon emission and detection devices and integrated photonics system

Strained semiconductor using elastic edge relaxation, a buried stressor layer and a sacrificial stressor layer

Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

Tensile strained semiconductor photon emission and detection devices and integrated photonics system

Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height

MIS contact structure with metal oxide conductor

Method of forming a field effect transistors with a sacrificial stressor layer and strained source and drain regions formed in recesses

Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor

Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)

SOI wafers and devices with buried stressor

Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation

Biaxial strained field effect transistor devices

Method of making a semiconductor device having a strained semiconductor active region using edge relaxation, a buried stressor layer and a sacrificial stressor layer

Strained silicon with elastic edge relaxation

Tensile strained semiconductor photon emission and detection devices and integrated photonics system

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

MIS contact structure with metal oxide conductor

ACORN SEMI LLC

Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

MIS contact structure with metal oxide conductor

Tensile strained semiconductor photon emission and detection devices and integrated photonics system

MIS contact structure with metal oxide conductor

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

SOI wafers and devices with buried stressors

Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers

Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers

Relating to SOI wafers and devices with buried stressors

Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

SOI wafers and devices with buried stressor

Tensile strained semiconductor photon emission and detection devices and integrated photonics system

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers

CLIFTON PAUL A

Tensile strained semiconductor photon emission and detection devices and integrated photonics system

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation

GRUPP DANIEL E

Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor

FAULKNER CARL M

Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s)

GOEBEL ANDREAS

Field effect transistor source or drain with a multi-facet surface

ACOM TECHNOLOGIES INC

Strained silicon with elastic edge relaxation

MATSUSHITA ELECTRIC INDUSTRIAL CO LTD

Semiconductor device