Inventor
PILLAY SANJAY
US21 patents
⚠️ This page may combine multiple inventors who share the name “PILLAY SANJAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
BANK OF AMERICA
11 patentsUS9898269B2Feb 20, 2018
Build deployment automation for information technology mangement
BANK OF AMERICA7 citations82
US9323513B2Apr 26, 2016
Build deployment automation for information technology management
BANK OF AMERICA12 citations82
US9521141B2Dec 13, 2016
Caller validation
BANK OF AMERICA4 citations72
US12153901B2Nov 26, 2024
Mobile application development device
BANK OF AMERICA0 citations60
US11977869B2May 7, 2024
Two-phase application development device
BANK OF AMERICA0 citations60
US11893362B2Feb 6, 2024
Mobile application development device
BANK OF AMERICA0 citations60
US11748075B2Sep 5, 2023
Two-phase application development device
BANK OF AMERICA0 citations60
US11635945B2Apr 25, 2023
Mobile application development device
BANK OF AMERICA0 citations60
US11403072B1Aug 2, 2022
Mobile application development device
BANK OF AMERICA0 citations60
US12175211B2Dec 24, 2024
System and method for creating configurational blocks used for building continuous real-time software logical sequences
BANK OF AMERICA0 citations45
US12141023B2Nov 12, 2024
System for monitoring computing server performance using an artificial intelligence-based plugin
BANK OF AMERICA0 citations45
CIRRUS LOGIC INC
4 patentsUS6847244B2Jan 25, 2005
Variable duty cycle clock generation circuits and methods and systems using the same
CIRRUS LOGIC INC28 citations86
US7747917B2Jun 29, 2010
Scan cells with minimized shoot-through and scan chains and integrated circuits using the same
CIRRUS LOGIC INC18 citations78
US6359315B1Mar 19, 2002
Circuits for controlling a bidirectional terminal and systems using the same
CIRRUS LOGIC INC2 citations62
US7596681B2Sep 29, 2009
Processor and processing method for reusing arbitrary sections of program code
CIRRUS LOGIC INC6 citations56
MENTOR GRAPHICS CORP
4 patentsUS10768227B2Sep 8, 2020
Systems and methods for analyzing failure rates due to soft/hard errors in the design of a digital electronic device
MENTOR GRAPHICS CORP2 citations67
US11036604B2Jun 15, 2021
Parallel fault simulator with back propagation enhancement
MENTOR GRAPHICS CORP0 citations57
US10796047B2Oct 6, 2020
Functional safety synthesis
MENTOR GRAPHICS CORP0 citations44
US10775430B2Sep 15, 2020
Fault campaign in mixed signal environment
MENTOR GRAPHICS CORP0 citations36
AUSTEMPER DESIGN SYSTEMS INC
2 patentsUS10522237B2Dec 31, 2019
Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation
AUSTEMPER DESIGN SYSTEMS INC0 citations45
US9991008B2Jun 5, 2018
Systems and methods for analyzing soft errors in a design and reducing the associated failure rates thereof
AUSTEMPER DESIGN SYSTEMS INC0 citations35