Inventor

ZHU FANGFANG

CN76 patents

⚠️ This page may combine multiple inventors who share the name “ZHU FANGFANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZHU FANGFANG

MICRON TECHNOLOGY INC

Enabling stripe-based operations for error recovery at a memory sub-system

Refreshing data stored at a memory component based on a memory component characteristic component

Internal management traffic regulation for memory sub-systems

Performing hybrid wear leveling operations based on a sub-total write counter

Scanning techniques for a media-management operation of a memory sub-system

Hardware based status collector acceleration engine for memory sub-system operations

Unmap data pattern for coarse mapping memory sub-system

Performing hybrid wear leveling operations based on a sub-total write counter

Buffer allocation for reducing block transit penalty

Multiple-pass programming of memory cells using temporary parity generation

Managing distribution of page addresses and partition numbers in a memory sub-system

Managing host input/output in a memory system executing a table flush

Memory cell voltage level selection

Selecting a write operation mode from multiple write operation modes

Apparatus with read level management and methods for operating the same

Scanning techniques for a media-management operation of a memory sub-system

Reset and replay of memory sub-system controller in a memory sub-system

Performing hybrid wear leveling operations based on a sub-total write counter

Refreshing data stored at a memory component based on a memory component characteristic component

Selecting a write operation mode from multiple write operation modes

Reset and replay of memory sub-system controller in a memory sub-system

Refreshing data stored at a memory component based on a memory component characteristic component

Buffer allocation for reducing block transit penalty

Multiple-pass programming of memory cells using temporary parity generation

Enabling multiple data capacity modes at a memory sub-system

Hardware based status collector acceleration engine for memory sub-system operations

Enabling stripe-based operations for error recovery at a memory sub-system

Dynamic partition command queues for a memory device

Automated voltage demarcation (VDM) adjustment for memory device

Concurrent command limiter for a memory system

Memory block programming using defectivity information

Hardware based status collector acceleration engine for memory sub-system operations

Concurrent command limiter for a memory system

Dynamic partition command queues for a memory device

Automated voltage demarcation (VDM) adjustment for memory device

Enabling multiple data capacity modes at a memory sub-system

Performing scrambling operations based on a physical block address of a memory sub-system

Performing error checking operations on encrypted write data in a memory sub-system

Unmap data pattern for coarse mapping memory sub-system

Temperature and inter-pulse delay factors for media management operations at a memory device

Generating error checking data for error detection during modification of data in a memory sub-system

Limiting hot-cold swap wear leveling

Generating error checking data for error detection during modification of data in a memory sub-system

Managing trim commands in a memory sub-system

Managing trim commands in a memory sub-system

Redundancy metadata media management at a memory sub-system

Management unit based media management operations in memory devices

Dual-address command management using content addressable memory

UNIV LELAND STANFORD JUNIOR

Site-specific integration of transgenes into human cells

GABA agonists and antagonists affect differentiation of hematopoietic stem cells and megakaryocyte progenitors